Lines Matching refs:I915_READ
179 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; in intel_pch_rawclk()
192 clkcfg = I915_READ(CLKCFG); in intel_hrawclk()
231 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; in intel_fdi_link_freq()
1108 line1 = I915_READ(reg) & line_mask; in pipe_dsl_stopped()
1110 line2 = I915_READ(reg) & line_mask; in pipe_dsl_stopped()
1142 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, in intel_wait_for_pipe_off()
1164 val = I915_READ(DPLL(pipe)); in assert_pll()
1227 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in assert_fdi_tx()
1230 u32 val = I915_READ(FDI_TX_CTL(pipe)); in assert_fdi_tx()
1246 val = I915_READ(FDI_RX_CTL(pipe)); in assert_fdi_rx()
1268 val = I915_READ(FDI_TX_CTL(pipe)); in assert_fdi_tx_pll_enabled()
1278 val = I915_READ(FDI_RX_CTL(pipe)); in assert_fdi_rx_pll()
1301 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; in assert_panel_unlocked()
1304 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) in assert_panel_unlocked()
1313 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) in assert_panel_unlocked()
1317 val = I915_READ(pp_reg); in assert_panel_unlocked()
1334 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; in assert_cursor()
1336 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; in assert_cursor()
1361 u32 val = I915_READ(PIPECONF(cpu_transcoder)); in assert_pipe()
1376 val = I915_READ(DSPCNTR(plane)); in assert_plane()
1394 u32 val = I915_READ(DSPCNTR(pipe)); in assert_planes_disabled()
1403 u32 val = I915_READ(DSPCNTR(i)); in assert_planes_disabled()
1420 u32 val = I915_READ(PLANE_CTL(pipe, sprite)); in assert_sprites_disabled()
1427 u32 val = I915_READ(SPCNTR(pipe, sprite)); in assert_sprites_disabled()
1433 u32 val = I915_READ(SPRCTL(pipe)); in assert_sprites_disabled()
1438 u32 val = I915_READ(DVSCNTR(pipe)); in assert_sprites_disabled()
1458 val = I915_READ(PCH_DREF_CONTROL); in ibx_assert_pch_refclk_enabled()
1470 val = I915_READ(PCH_TRANSCONF(pipe)); in assert_pch_transcoder_disabled()
1485 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); in dp_pipe_enabled()
1551 u32 val = I915_READ(reg); in assert_pch_dp_disabled()
1564 u32 val = I915_READ(reg); in assert_pch_hdmi_disabled()
1583 val = I915_READ(PCH_ADPA); in assert_pch_ports_disabled()
1588 val = I915_READ(PCH_LVDS); in assert_pch_ports_disabled()
1619 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) in vlv_enable_pll()
1668 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) in chv_enable_pll()
1714 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); in i9xx_enable_pll()
1774 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()
1776 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()
1861 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) in vlv_wait_port_ready()
1863 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); in vlv_wait_port_ready()
1983 val = I915_READ(reg); in ironlake_enable_pch_transcoder()
1989 val = I915_READ(reg); in ironlake_enable_pch_transcoder()
1990 pipeconf_val = I915_READ(PIPECONF(pipe)); in ironlake_enable_pch_transcoder()
2016 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) in ironlake_enable_pch_transcoder()
2033 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder()
2038 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); in lpt_enable_pch_transcoder()
2047 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) in lpt_enable_pch_transcoder()
2065 val = I915_READ(reg); in ironlake_disable_pch_transcoder()
2069 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) in ironlake_disable_pch_transcoder()
2075 val = I915_READ(reg); in ironlake_disable_pch_transcoder()
2085 val = I915_READ(LPT_TRANSCONF); in lpt_disable_pch_transcoder()
2089 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) in lpt_disable_pch_transcoder()
2093 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); in lpt_disable_pch_transcoder()
2148 val = I915_READ(reg); in intel_enable_pipe()
2188 val = I915_READ(reg); in intel_disable_pipe()
3408 temp = I915_READ(reg); in intel_fdi_normal_train()
3419 temp = I915_READ(reg); in intel_fdi_normal_train()
3435 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | in intel_fdi_normal_train()
3454 temp = I915_READ(reg); in ironlake_fdi_link_train()
3458 I915_READ(reg); in ironlake_fdi_link_train()
3463 temp = I915_READ(reg); in ironlake_fdi_link_train()
3471 temp = I915_READ(reg); in ironlake_fdi_link_train()
3486 temp = I915_READ(reg); in ironlake_fdi_link_train()
3500 temp = I915_READ(reg); in ironlake_fdi_link_train()
3506 temp = I915_READ(reg); in ironlake_fdi_link_train()
3516 temp = I915_READ(reg); in ironlake_fdi_link_train()
3551 temp = I915_READ(reg); in gen6_fdi_link_train()
3561 temp = I915_READ(reg); in gen6_fdi_link_train()
3575 temp = I915_READ(reg); in gen6_fdi_link_train()
3590 temp = I915_READ(reg); in gen6_fdi_link_train()
3600 temp = I915_READ(reg); in gen6_fdi_link_train()
3617 temp = I915_READ(reg); in gen6_fdi_link_train()
3628 temp = I915_READ(reg); in gen6_fdi_link_train()
3643 temp = I915_READ(reg); in gen6_fdi_link_train()
3653 temp = I915_READ(reg); in gen6_fdi_link_train()
3683 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3692 I915_READ(FDI_RX_IIR(pipe))); in ivb_manual_fdi_link_train()
3698 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3704 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3712 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3725 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3735 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3739 (I915_READ(reg) & FDI_RX_BIT_LOCK)) { in ivb_manual_fdi_link_train()
3754 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3760 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3770 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3774 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { in ivb_manual_fdi_link_train()
3800 temp = I915_READ(reg); in ironlake_fdi_pll_enable()
3803 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_pll_enable()
3810 temp = I915_READ(reg); in ironlake_fdi_pll_enable()
3818 temp = I915_READ(reg); in ironlake_fdi_pll_enable()
3836 temp = I915_READ(reg); in ironlake_fdi_pll_disable()
3841 temp = I915_READ(reg); in ironlake_fdi_pll_disable()
3848 temp = I915_READ(reg); in ironlake_fdi_pll_disable()
3866 temp = I915_READ(reg); in ironlake_fdi_disable()
3871 temp = I915_READ(reg); in ironlake_fdi_disable()
3873 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
3885 temp = I915_READ(reg); in ironlake_fdi_disable()
3891 temp = I915_READ(reg); in ironlake_fdi_disable()
3901 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
4078 I915_READ(HTOTAL(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
4080 I915_READ(HBLANK(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
4082 I915_READ(HSYNC(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
4085 I915_READ(VTOTAL(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
4087 I915_READ(VBLANK(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
4089 I915_READ(VSYNC(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
4091 I915_READ(VSYNCSHIFT(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
4099 temp = I915_READ(SOUTH_CHICKEN1); in cpt_set_fdi_bc_bifurcation()
4103 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); in cpt_set_fdi_bc_bifurcation()
4104 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); in cpt_set_fdi_bc_bifurcation()
4162 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); in ironlake_pch_enable()
4172 temp = I915_READ(PCH_DPLL_SEL); in ironlake_pch_enable()
4199 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; in ironlake_pch_enable()
4201 temp = I915_READ(reg); in ironlake_pch_enable()
4363 temp = I915_READ(dslreg); in cpt_verify_modeset()
4365 if (wait_for(I915_READ(dslreg) != temp, 5)) { in cpt_verify_modeset()
4366 if (wait_for(I915_READ(dslreg) != temp, 5)) in cpt_verify_modeset()
4627 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) in hsw_disable_ips()
4663 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == in intel_crtc_load_lut()
5112 temp = I915_READ(reg); in ironlake_crtc_disable()
5119 temp = I915_READ(PCH_DPLL_SEL); in ironlake_crtc_disable()
5187 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); in i9xx_pfit_enable()
5399 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; in intel_update_max_cdclk()
5416 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) in intel_update_max_cdclk()
5524 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; in broxton_set_cdclk()
5538 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), in broxton_set_cdclk()
5546 val = I915_READ(BXT_DE_PLL_CTL); in broxton_set_cdclk()
5553 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) in broxton_set_cdclk()
5556 val = I915_READ(CDCLK_CTL); in broxton_set_cdclk()
5598 val = I915_READ(HSW_NDE_RSTWRN_OPT); in broxton_init_cdclk()
5606 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { in broxton_init_cdclk()
5620 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); in broxton_init_cdclk()
5625 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) in broxton_init_cdclk()
5633 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); in broxton_uninit_cdclk()
5638 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) in broxton_uninit_cdclk()
5686 val = I915_READ(CDCLK_CTL); in skl_dpll0_enable()
5709 val = I915_READ(DPLL_CTRL1); in skl_dpll0_enable()
5724 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); in skl_dpll0_enable()
5726 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) in skl_dpll0_enable()
5807 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); in skl_uninit_cdclk()
5812 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) in skl_uninit_cdclk()
5820 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & in skl_uninit_cdclk()
5822 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) in skl_uninit_cdclk()
5835 val = I915_READ(HSW_NDE_RSTWRN_OPT); in skl_init_cdclk()
5842 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { in skl_init_cdclk()
5852 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); in skl_init_cdclk()
5857 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) in skl_init_cdclk()
6105 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); in vlv_program_pfi_credits()
6263 I915_READ(PFIT_CONTROL)); in i9xx_pfit_disable()
6702 uint32_t lcpll1 = I915_READ(LCPLL1_CTL); in skylake_get_display_clock_speed()
6703 uint32_t cdctl = I915_READ(CDCLK_CTL); in skylake_get_display_clock_speed()
6712 linkrate = (I915_READ(DPLL_CTRL1) & in skylake_get_display_clock_speed()
6749 uint32_t cdctl = I915_READ(CDCLK_CTL); in broxton_get_display_clock_speed()
6750 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; in broxton_get_display_clock_speed()
6751 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); in broxton_get_display_clock_speed()
6777 uint32_t lcpll = I915_READ(LCPLL_CTL); in broadwell_get_display_clock_speed()
6782 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) in broadwell_get_display_clock_speed()
6797 uint32_t lcpll = I915_READ(LCPLL_CTL); in haswell_get_display_clock_speed()
6802 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) in haswell_get_display_clock_speed()
6986 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); in intel_hpll_vco()
7754 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); in intel_set_pipe_timings()
7772 tmp = I915_READ(HTOTAL(cpu_transcoder)); in intel_get_pipe_timings()
7775 tmp = I915_READ(HBLANK(cpu_transcoder)); in intel_get_pipe_timings()
7778 tmp = I915_READ(HSYNC(cpu_transcoder)); in intel_get_pipe_timings()
7782 tmp = I915_READ(VTOTAL(cpu_transcoder)); in intel_get_pipe_timings()
7785 tmp = I915_READ(VBLANK(cpu_transcoder)); in intel_get_pipe_timings()
7788 tmp = I915_READ(VSYNC(cpu_transcoder)); in intel_get_pipe_timings()
7792 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { in intel_get_pipe_timings()
7798 tmp = I915_READ(PIPESRC(crtc->pipe)); in intel_get_pipe_timings()
7840 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; in i9xx_set_pipeconf()
7983 tmp = I915_READ(PFIT_CONTROL); in i9xx_get_pfit_config()
7997 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); in i9xx_get_pfit_config()
8000 I915_READ(LVDS) & LVDS_BORDER_ENABLE; in i9xx_get_pfit_config()
8043 val = I915_READ(DSPCNTR(plane)); in i9xx_get_initial_plane_config()
8069 offset = I915_READ(DSPTILEOFF(plane)); in i9xx_get_initial_plane_config()
8071 offset = I915_READ(DSPLINOFF(plane)); in i9xx_get_initial_plane_config()
8072 base = I915_READ(DSPSURF(plane)) & 0xfffff000; in i9xx_get_initial_plane_config()
8074 base = I915_READ(DSPADDR(plane)); in i9xx_get_initial_plane_config()
8078 val = I915_READ(PIPESRC(pipe)); in i9xx_get_initial_plane_config()
8082 val = I915_READ(DSPSTRIDE(pipe)); in i9xx_get_initial_plane_config()
8143 tmp = I915_READ(PIPECONF(crtc->pipe)); in i9xx_get_pipe_config()
8174 tmp = I915_READ(DPLL_MD(crtc->pipe)); in i9xx_get_pipe_config()
8180 tmp = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
8190 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
8200 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); in i9xx_get_pipe_config()
8201 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); in i9xx_get_pipe_config()
8271 val = I915_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()
8379 tmp = I915_READ(SOUTH_CHICKEN2); in lpt_reset_fdi_mphy()
8383 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & in lpt_reset_fdi_mphy()
8387 tmp = I915_READ(SOUTH_CHICKEN2); in lpt_reset_fdi_mphy()
8391 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & in lpt_reset_fdi_mphy()
8984 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); in intel_pch_transcoder_get_m_n()
8985 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); in intel_pch_transcoder_get_m_n()
8986 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) in intel_pch_transcoder_get_m_n()
8988 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); in intel_pch_transcoder_get_m_n()
8989 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) in intel_pch_transcoder_get_m_n()
9003 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); in intel_cpu_transcoder_get_m_n()
9004 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); in intel_cpu_transcoder_get_m_n()
9005 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) in intel_cpu_transcoder_get_m_n()
9007 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); in intel_cpu_transcoder_get_m_n()
9008 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) in intel_cpu_transcoder_get_m_n()
9016 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); in intel_cpu_transcoder_get_m_n()
9017 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); in intel_cpu_transcoder_get_m_n()
9018 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) in intel_cpu_transcoder_get_m_n()
9020 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); in intel_cpu_transcoder_get_m_n()
9021 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) in intel_cpu_transcoder_get_m_n()
9025 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
9026 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
9027 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) in intel_cpu_transcoder_get_m_n()
9029 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
9030 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) in intel_cpu_transcoder_get_m_n()
9065 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); in skylake_get_pfit_config()
9069 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); in skylake_get_pfit_config()
9070 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); in skylake_get_pfit_config()
9104 val = I915_READ(PLANE_CTL(pipe, 0)); in skylake_get_initial_plane_config()
9135 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; in skylake_get_initial_plane_config()
9138 offset = I915_READ(PLANE_OFFSET(pipe, 0)); in skylake_get_initial_plane_config()
9140 val = I915_READ(PLANE_SIZE(pipe, 0)); in skylake_get_initial_plane_config()
9144 val = I915_READ(PLANE_STRIDE(pipe, 0)); in skylake_get_initial_plane_config()
9174 tmp = I915_READ(PF_CTL(crtc->pipe)); in ironlake_get_pfit_config()
9178 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); in ironlake_get_pfit_config()
9179 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); in ironlake_get_pfit_config()
9204 val = I915_READ(DSPCNTR(pipe)); in ironlake_get_initial_plane_config()
9228 base = I915_READ(DSPSURF(pipe)) & 0xfffff000; in ironlake_get_initial_plane_config()
9230 offset = I915_READ(DSPOFFSET(pipe)); in ironlake_get_initial_plane_config()
9233 offset = I915_READ(DSPTILEOFF(pipe)); in ironlake_get_initial_plane_config()
9235 offset = I915_READ(DSPLINOFF(pipe)); in ironlake_get_initial_plane_config()
9239 val = I915_READ(PIPESRC(pipe)); in ironlake_get_initial_plane_config()
9243 val = I915_READ(DSPSTRIDE(pipe)); in ironlake_get_initial_plane_config()
9274 tmp = I915_READ(PIPECONF(crtc->pipe)); in ironlake_get_pipe_config()
9298 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { in ironlake_get_pipe_config()
9303 tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); in ironlake_get_pipe_config()
9313 tmp = I915_READ(PCH_DPLL_SEL); in ironlake_get_pipe_config()
9351 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); in assert_can_disable_lcpll()
9352 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); in assert_can_disable_lcpll()
9353 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); in assert_can_disable_lcpll()
9354 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); in assert_can_disable_lcpll()
9355 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); in assert_can_disable_lcpll()
9356 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, in assert_can_disable_lcpll()
9359 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, in assert_can_disable_lcpll()
9361 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, in assert_can_disable_lcpll()
9363 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, in assert_can_disable_lcpll()
9365 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); in assert_can_disable_lcpll()
9381 return I915_READ(D_COMP_HSW); in hsw_read_dcomp()
9383 return I915_READ(D_COMP_BDW); in hsw_read_dcomp()
9417 val = I915_READ(LCPLL_CTL); in hsw_disable_lcpll()
9423 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & in hsw_disable_lcpll()
9427 val = I915_READ(LCPLL_CTL); in hsw_disable_lcpll()
9434 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) in hsw_disable_lcpll()
9447 val = I915_READ(LCPLL_CTL); in hsw_disable_lcpll()
9462 val = I915_READ(LCPLL_CTL); in hsw_restore_lcpll()
9485 val = I915_READ(LCPLL_CTL); in hsw_restore_lcpll()
9489 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) in hsw_restore_lcpll()
9493 val = I915_READ(LCPLL_CTL); in hsw_restore_lcpll()
9497 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & in hsw_restore_lcpll()
9537 val = I915_READ(SOUTH_DSPCLK_GATE_D); in hsw_enable_pc8()
9557 val = I915_READ(SOUTH_DSPCLK_GATE_D); in hsw_disable_pc8()
9608 if (WARN((I915_READ(LCPLL_CTL) & in broadwell_set_cdclk()
9625 val = I915_READ(LCPLL_CTL); in broadwell_set_cdclk()
9629 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & in broadwell_set_cdclk()
9633 val = I915_READ(LCPLL_CTL); in broadwell_set_cdclk()
9660 val = I915_READ(LCPLL_CTL); in broadwell_set_cdclk()
9664 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & in broadwell_set_cdclk()
9760 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); in skylake_get_ddi_pll()
9770 dpll_ctl1 = I915_READ(DPLL_CTRL1); in skylake_get_ddi_pll()
9789 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); in haswell_get_ddi_pll()
9812 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); in haswell_get_ddi_port_state()
9836 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { in haswell_get_ddi_port_state()
9839 tmp = I915_READ(FDI_RX_CTL(PIPE_A)); in haswell_get_ddi_port_state()
9862 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); in haswell_get_pipe_config()
9888 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); in haswell_get_pipe_config()
9916 (I915_READ(IPS_CTL) & IPS_ENABLE); in haswell_get_pipe_config()
9920 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; in haswell_get_pipe_config()
10597 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); in i9xx_crtc_clock_get()
10679 int htot = I915_READ(HTOTAL(cpu_transcoder)); in intel_crtc_mode_get()
10680 int hsync = I915_READ(HSYNC(cpu_transcoder)); in intel_crtc_mode_get()
10681 int vtot = I915_READ(VTOTAL(cpu_transcoder)); in intel_crtc_mode_get()
10682 int vsync = I915_READ(VSYNC(cpu_transcoder)); in intel_crtc_mode_get()
10698 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); in intel_crtc_mode_get()
10699 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); in intel_crtc_mode_get()
10700 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); in intel_crtc_mode_get()
10880 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == in page_flip_finished()
10882 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), in page_flip_finished()
11016 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; in intel_gen4_queue_flip()
11052 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; in intel_gen6_queue_flip()
11190 ctl = I915_READ(PLANE_CTL(pipe, 0)); in skl_do_mmio_flip()
11239 dspcntr = I915_READ(reg); in ilk_do_mmio_flip()
11361 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); in __intel_pageflip_stall_check()
11363 addr = I915_READ(DSPADDR(intel_crtc->plane)); in __intel_pageflip_stall_check()
11494 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; in intel_crtc_page_flip()
13347 val = I915_READ(PCH_DPLL(pll->id)); in ibx_pch_dpll_get_hw_state()
13349 hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); in ibx_pch_dpll_get_hw_state()
13350 hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); in ibx_pch_dpll_get_hw_state()
14043 if ((I915_READ(DP_A) & DP_DETECTED) == 0) in has_edp_a()
14046 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) in has_edp_a()
14099 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; in intel_setup_outputs()
14106 found = I915_READ(SFUSE_STRAP); in intel_setup_outputs()
14130 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { in intel_setup_outputs()
14135 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) in intel_setup_outputs()
14139 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) in intel_setup_outputs()
14142 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) in intel_setup_outputs()
14145 if (I915_READ(PCH_DP_C) & DP_DETECTED) in intel_setup_outputs()
14148 if (I915_READ(PCH_DP_D) & DP_DETECTED) in intel_setup_outputs()
14160 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && in intel_setup_outputs()
14163 if (I915_READ(VLV_DP_B) & DP_DETECTED || in intel_setup_outputs()
14167 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && in intel_setup_outputs()
14170 if (I915_READ(VLV_DP_C) & DP_DETECTED || in intel_setup_outputs()
14176 if (I915_READ(CHV_HDMID) & SDVO_DETECTED) in intel_setup_outputs()
14178 if (I915_READ(CHV_DP_D) & DP_DETECTED) in intel_setup_outputs()
14186 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { in intel_setup_outputs()
14200 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { in intel_setup_outputs()
14205 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { in intel_setup_outputs()
14216 (I915_READ(DP_D) & DP_DETECTED)) in intel_setup_outputs()
14907 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & in intel_modeset_init()
15033 val = I915_READ(DSPCNTR(!crtc->plane)); in intel_check_plane_mapping()
15061 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); in intel_sanitize_crtc()
15216 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { in i915_redisable_vga_power_on()
15243 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; in primary_get_hw_state()
15694 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); in intel_display_capture_error_state()
15703 error->cursor[i].control = I915_READ(CURCNTR(i)); in intel_display_capture_error_state()
15704 error->cursor[i].position = I915_READ(CURPOS(i)); in intel_display_capture_error_state()
15705 error->cursor[i].base = I915_READ(CURBASE(i)); in intel_display_capture_error_state()
15707 error->plane[i].control = I915_READ(DSPCNTR(i)); in intel_display_capture_error_state()
15708 error->plane[i].stride = I915_READ(DSPSTRIDE(i)); in intel_display_capture_error_state()
15710 error->plane[i].size = I915_READ(DSPSIZE(i)); in intel_display_capture_error_state()
15711 error->plane[i].pos = I915_READ(DSPPOS(i)); in intel_display_capture_error_state()
15714 error->plane[i].addr = I915_READ(DSPADDR(i)); in intel_display_capture_error_state()
15716 error->plane[i].surface = I915_READ(DSPSURF(i)); in intel_display_capture_error_state()
15717 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); in intel_display_capture_error_state()
15720 error->pipe[i].source = I915_READ(PIPESRC(i)); in intel_display_capture_error_state()
15723 error->pipe[i].stat = I915_READ(PIPESTAT(i)); in intel_display_capture_error_state()
15741 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); in intel_display_capture_error_state()
15742 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); in intel_display_capture_error_state()
15743 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); in intel_display_capture_error_state()
15744 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); in intel_display_capture_error_state()
15745 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); in intel_display_capture_error_state()
15746 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); in intel_display_capture_error_state()
15747 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); in intel_display_capture_error_state()