1615 	I915_WRITE(reg, dpll);  in vlv_enable_pll()
1622 	I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);  in vlv_enable_pll()
1626 	I915_WRITE(reg, dpll);  in vlv_enable_pll()
1629 	I915_WRITE(reg, dpll);  in vlv_enable_pll()
1632 	I915_WRITE(reg, dpll);  in vlv_enable_pll()
1665 	I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);  in chv_enable_pll()
1672 	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);  in chv_enable_pll()
1713 		I915_WRITE(DPLL(!crtc->pipe),  in i9xx_enable_pll()
1722 	I915_WRITE(reg, 0);  in i9xx_enable_pll()
1724 	I915_WRITE(reg, dpll);  in i9xx_enable_pll()
1731 		I915_WRITE(DPLL_MD(crtc->pipe),  in i9xx_enable_pll()
1739 		I915_WRITE(reg, dpll);  in i9xx_enable_pll()
1743 	I915_WRITE(reg, dpll);  in i9xx_enable_pll()
1746 	I915_WRITE(reg, dpll);  in i9xx_enable_pll()
1749 	I915_WRITE(reg, dpll);  in i9xx_enable_pll()
1773 		I915_WRITE(DPLL(PIPE_B),  in i9xx_disable_pll()
1775 		I915_WRITE(DPLL(PIPE_A),  in i9xx_disable_pll()
1787 	I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);  in i9xx_disable_pll()
1805 	I915_WRITE(DPLL(pipe), val);  in vlv_disable_pll()
1823 	I915_WRITE(DPLL(pipe), val);  in chv_disable_pll()
1985 		I915_WRITE(reg, val);  in ironlake_enable_pch_transcoder()
2015 	I915_WRITE(reg, val | TRANS_ENABLE);  in ironlake_enable_pch_transcoder()
2035 	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);  in lpt_enable_pch_transcoder()
2046 	I915_WRITE(LPT_TRANSCONF, val);  in lpt_enable_pch_transcoder()
2067 	I915_WRITE(reg, val);  in ironlake_disable_pch_transcoder()
2077 		I915_WRITE(reg, val);  in ironlake_disable_pch_transcoder()
2087 	I915_WRITE(LPT_TRANSCONF, val);  in lpt_disable_pch_transcoder()
2095 	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);  in lpt_disable_pch_transcoder()
2155 	I915_WRITE(reg, val | PIPECONF_ENABLE);  in intel_enable_pipe()
2204 	I915_WRITE(reg, val);  in intel_disable_pipe()
2702 		I915_WRITE(reg, 0);  in i9xx_update_primary_plane()
2704 			I915_WRITE(DSPSURF(plane), 0);  in i9xx_update_primary_plane()
2706 			I915_WRITE(DSPADDR(plane), 0);  in i9xx_update_primary_plane()
2728 		I915_WRITE(DSPSIZE(plane),  in i9xx_update_primary_plane()
2731 		I915_WRITE(DSPPOS(plane), 0);  in i9xx_update_primary_plane()
2733 		I915_WRITE(PRIMSIZE(plane),  in i9xx_update_primary_plane()
2736 		I915_WRITE(PRIMPOS(plane), 0);  in i9xx_update_primary_plane()
2737 		I915_WRITE(PRIMCNSTALPHA(plane), 0);  in i9xx_update_primary_plane()
2802 	I915_WRITE(reg, dspcntr);  in i9xx_update_primary_plane()
2804 	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);  in i9xx_update_primary_plane()
2806 		I915_WRITE(DSPSURF(plane),  in i9xx_update_primary_plane()
2808 		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);  in i9xx_update_primary_plane()
2809 		I915_WRITE(DSPLINOFF(plane), linear_offset);  in i9xx_update_primary_plane()
2811 		I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);  in i9xx_update_primary_plane()
2832 		I915_WRITE(reg, 0);  in ironlake_update_primary_plane()
2833 		I915_WRITE(DSPSURF(plane), 0);  in ironlake_update_primary_plane()
2905 	I915_WRITE(reg, dspcntr);  in ironlake_update_primary_plane()
2907 	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);  in ironlake_update_primary_plane()
2908 	I915_WRITE(DSPSURF(plane),  in ironlake_update_primary_plane()
2911 		I915_WRITE(DSPOFFSET(plane), (y << 16) | x);  in ironlake_update_primary_plane()
2913 		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);  in ironlake_update_primary_plane()
2914 		I915_WRITE(DSPLINOFF(plane), linear_offset);  in ironlake_update_primary_plane()
2984 	I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);  in skl_detach_scaler()
2985 	I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);  in skl_detach_scaler()
2986 	I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);  in skl_detach_scaler()
3112 		I915_WRITE(PLANE_CTL(pipe, 0), 0);  in skylake_update_primary_plane()
3113 		I915_WRITE(PLANE_SURF(pipe, 0), 0);  in skylake_update_primary_plane()
3167 	I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);  in skylake_update_primary_plane()
3168 	I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);  in skylake_update_primary_plane()
3169 	I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);  in skylake_update_primary_plane()
3170 	I915_WRITE(PLANE_STRIDE(pipe, 0), stride);  in skylake_update_primary_plane()
3178 		I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);  in skylake_update_primary_plane()
3179 		I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);  in skylake_update_primary_plane()
3180 		I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);  in skylake_update_primary_plane()
3181 		I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);  in skylake_update_primary_plane()
3182 		I915_WRITE(PLANE_POS(pipe, 0), 0);  in skylake_update_primary_plane()
3184 		I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);  in skylake_update_primary_plane()
3187 	I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);  in skylake_update_primary_plane()
3380 	I915_WRITE(PIPESRC(crtc->pipe),  in intel_update_pipe_config()
3416 	I915_WRITE(reg, temp);  in intel_fdi_normal_train()
3427 	I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);  in intel_fdi_normal_train()
3435 		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |  in intel_fdi_normal_train()
3457 	I915_WRITE(reg, temp);  in ironlake_fdi_link_train()
3468 	I915_WRITE(reg, temp | FDI_TX_ENABLE);  in ironlake_fdi_link_train()
3474 	I915_WRITE(reg, temp | FDI_RX_ENABLE);  in ironlake_fdi_link_train()
3480 	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);  in ironlake_fdi_link_train()
3481 	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |  in ironlake_fdi_link_train()
3491 			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);  in ironlake_fdi_link_train()
3503 	I915_WRITE(reg, temp);  in ironlake_fdi_link_train()
3509 	I915_WRITE(reg, temp);  in ironlake_fdi_link_train()
3520 			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);  in ironlake_fdi_link_train()
3554 	I915_WRITE(reg, temp);  in gen6_fdi_link_train()
3569 	I915_WRITE(reg, temp | FDI_TX_ENABLE);  in gen6_fdi_link_train()
3571 	I915_WRITE(FDI_RX_MISC(pipe),  in gen6_fdi_link_train()
3583 	I915_WRITE(reg, temp | FDI_RX_ENABLE);  in gen6_fdi_link_train()
3593 		I915_WRITE(reg, temp);  in gen6_fdi_link_train()
3603 				I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);  in gen6_fdi_link_train()
3625 	I915_WRITE(reg, temp);  in gen6_fdi_link_train()
3636 	I915_WRITE(reg, temp);  in gen6_fdi_link_train()
3646 		I915_WRITE(reg, temp);  in gen6_fdi_link_train()
3656 				I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);  in gen6_fdi_link_train()
3686 	I915_WRITE(reg, temp);  in ivb_manual_fdi_link_train()
3701 		I915_WRITE(reg, temp);  in ivb_manual_fdi_link_train()
3708 		I915_WRITE(reg, temp);  in ivb_manual_fdi_link_train()
3719 		I915_WRITE(reg, temp | FDI_TX_ENABLE);  in ivb_manual_fdi_link_train()
3721 		I915_WRITE(FDI_RX_MISC(pipe),  in ivb_manual_fdi_link_train()
3728 		I915_WRITE(reg, temp | FDI_RX_ENABLE);  in ivb_manual_fdi_link_train()
3740 				I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);  in ivb_manual_fdi_link_train()
3757 		I915_WRITE(reg, temp);  in ivb_manual_fdi_link_train()
3763 		I915_WRITE(reg, temp);  in ivb_manual_fdi_link_train()
3775 				I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);  in ivb_manual_fdi_link_train()
3804 	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);  in ironlake_fdi_pll_enable()
3811 	I915_WRITE(reg, temp | FDI_PCDCLK);  in ironlake_fdi_pll_enable()
3820 		I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);  in ironlake_fdi_pll_enable()
3837 	I915_WRITE(reg, temp & ~FDI_PCDCLK);  in ironlake_fdi_pll_disable()
3842 	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);  in ironlake_fdi_pll_disable()
3849 	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);  in ironlake_fdi_pll_disable()
3867 	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);  in ironlake_fdi_disable()
3874 	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);  in ironlake_fdi_disable()
3881 		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);  in ironlake_fdi_disable()
3888 	I915_WRITE(reg, temp);  in ironlake_fdi_disable()
3902 	I915_WRITE(reg, temp);  in ironlake_fdi_disable()
3995 	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);  in lpt_program_iclkip()
4065 	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);  in lpt_program_iclkip()
4077 	I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),  in ironlake_pch_transcoder_set_timings()
4079 	I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),  in ironlake_pch_transcoder_set_timings()
4081 	I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),  in ironlake_pch_transcoder_set_timings()
4084 	I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),  in ironlake_pch_transcoder_set_timings()
4086 	I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),  in ironlake_pch_transcoder_set_timings()
4088 	I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),  in ironlake_pch_transcoder_set_timings()
4090 	I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),  in ironlake_pch_transcoder_set_timings()
4111 	I915_WRITE(SOUTH_CHICKEN1, temp);  in cpt_set_fdi_bc_bifurcation()
4161 	I915_WRITE(FDI_RX_TUSIZE1(pipe),  in ironlake_pch_enable()
4179 		I915_WRITE(PCH_DPLL_SEL, temp);  in ironlake_pch_enable()
4227 		I915_WRITE(reg, temp);  in ironlake_pch_enable()
4550 		I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |  in skylake_pfit_enable()
4552 		I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);  in skylake_pfit_enable()
4553 		I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);  in skylake_pfit_enable()
4571 			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |  in ironlake_pfit_enable()
4574 			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);  in ironlake_pfit_enable()
4575 		I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);  in ironlake_pfit_enable()
4576 		I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);  in ironlake_pfit_enable()
4602 		I915_WRITE(IPS_CTL, IPS_ENABLE);  in hsw_enable_ips()
4630 		I915_WRITE(IPS_CTL, 0);  in hsw_disable_ips()
4677 		I915_WRITE(palreg,  in intel_crtc_load_lut()
4989 		I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),  in haswell_crtc_enable()
5071 		I915_WRITE(PF_CTL(pipe), 0);  in ironlake_pfit_disable()
5072 		I915_WRITE(PF_WIN_POS(pipe), 0);  in ironlake_pfit_disable()
5073 		I915_WRITE(PF_WIN_SZ(pipe), 0);  in ironlake_pfit_disable()
5116 			I915_WRITE(reg, temp);  in ironlake_crtc_disable()
5121 			I915_WRITE(PCH_DPLL_SEL, temp);  in ironlake_crtc_disable()
5190 	I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);  in i9xx_pfit_enable()
5191 	I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);  in i9xx_pfit_enable()
5195 	I915_WRITE(BCLRPAT(crtc->pipe), 0);  in i9xx_pfit_enable()
5461 		I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));  in intel_update_cdclk()
5536 		I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);  in broxton_set_cdclk()
5549 		I915_WRITE(BXT_DE_PLL_CTL, val);  in broxton_set_cdclk()
5551 		I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);  in broxton_set_cdclk()
5570 		I915_WRITE(CDCLK_CTL, val);  in broxton_set_cdclk()
5600 	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);  in broxton_init_cdclk()
5620 	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);  in broxton_init_cdclk()
5633 	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);  in broxton_uninit_cdclk()
5697 	I915_WRITE(CDCLK_CTL, val);  in skl_dpll0_enable()
5721 	I915_WRITE(DPLL_CTRL1, val);  in skl_dpll0_enable()
5724 	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);  in skl_dpll0_enable()
5793 	I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));  in skl_set_cdclk()
5807 	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);  in skl_uninit_cdclk()
5820 		I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &  in skl_uninit_cdclk()
5836 	I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);  in skl_init_cdclk()
5852 	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);  in skl_init_cdclk()
6095 	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |  in vlv_program_pfi_credits()
6098 	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |  in vlv_program_pfi_credits()
6157 		I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);  in valleyview_crtc_enable()
6158 		I915_WRITE(CHV_CANVAS(pipe), 0);  in valleyview_crtc_enable()
6203 	I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);  in i9xx_set_pll_dividers()
6204 	I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);  in i9xx_set_pll_dividers()
6264 	I915_WRITE(PFIT_CONTROL, 0);  in i9xx_pfit_disable()
7237 	I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);  in intel_pch_transcoder_set_m_n()
7238 	I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);  in intel_pch_transcoder_set_m_n()
7239 	I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);  in intel_pch_transcoder_set_m_n()
7240 	I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);  in intel_pch_transcoder_set_m_n()
7253 		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);  in intel_cpu_transcoder_set_m_n()
7254 		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);  in intel_cpu_transcoder_set_m_n()
7255 		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);  in intel_cpu_transcoder_set_m_n()
7256 		I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);  in intel_cpu_transcoder_set_m_n()
7263 			I915_WRITE(PIPE_DATA_M2(transcoder),  in intel_cpu_transcoder_set_m_n()
7265 			I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);  in intel_cpu_transcoder_set_m_n()
7266 			I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);  in intel_cpu_transcoder_set_m_n()
7267 			I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);  in intel_cpu_transcoder_set_m_n()
7270 		I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);  in intel_cpu_transcoder_set_m_n()
7271 		I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);  in intel_cpu_transcoder_set_m_n()
7272 		I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);  in intel_cpu_transcoder_set_m_n()
7273 		I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);  in intel_cpu_transcoder_set_m_n()
7455 	I915_WRITE(dpll_reg,  in chv_prepare_pll()
7726 		I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);  in intel_set_pipe_timings()
7728 	I915_WRITE(HTOTAL(cpu_transcoder),  in intel_set_pipe_timings()
7731 	I915_WRITE(HBLANK(cpu_transcoder),  in intel_set_pipe_timings()
7734 	I915_WRITE(HSYNC(cpu_transcoder),  in intel_set_pipe_timings()
7738 	I915_WRITE(VTOTAL(cpu_transcoder),  in intel_set_pipe_timings()
7741 	I915_WRITE(VBLANK(cpu_transcoder),  in intel_set_pipe_timings()
7744 	I915_WRITE(VSYNC(cpu_transcoder),  in intel_set_pipe_timings()
7754 		I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));  in intel_set_pipe_timings()
7759 	I915_WRITE(PIPESRC(pipe),  in intel_set_pipe_timings()
7889 	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);  in i9xx_set_pipeconf()
8329 		I915_WRITE(PCH_DREF_CONTROL, val);  in ironlake_init_pch_refclk()
8345 		I915_WRITE(PCH_DREF_CONTROL, val);  in ironlake_init_pch_refclk()
8356 		I915_WRITE(PCH_DREF_CONTROL, val);  in ironlake_init_pch_refclk()
8367 		I915_WRITE(PCH_DREF_CONTROL, val);  in ironlake_init_pch_refclk()
8381 	I915_WRITE(SOUTH_CHICKEN2, tmp);  in lpt_reset_fdi_mphy()
8389 	I915_WRITE(SOUTH_CHICKEN2, tmp);  in lpt_reset_fdi_mphy()
8649 	I915_WRITE(PIPECONF(pipe), val);  in ironlake_set_pipeconf()
8683 	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);  in intel_set_pipe_csc()
8684 	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);  in intel_set_pipe_csc()
8686 	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);  in intel_set_pipe_csc()
8687 	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);  in intel_set_pipe_csc()
8689 	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);  in intel_set_pipe_csc()
8690 	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);  in intel_set_pipe_csc()
8692 	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);  in intel_set_pipe_csc()
8693 	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);  in intel_set_pipe_csc()
8694 	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);  in intel_set_pipe_csc()
8702 		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);  in intel_set_pipe_csc()
8703 		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);  in intel_set_pipe_csc()
8704 		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);  in intel_set_pipe_csc()
8706 		I915_WRITE(PIPE_CSC_MODE(pipe), 0);  in intel_set_pipe_csc()
8713 		I915_WRITE(PIPE_CSC_MODE(pipe), mode);  in intel_set_pipe_csc()
8736 	I915_WRITE(PIPECONF(cpu_transcoder), val);  in haswell_set_pipeconf()
8739 	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);  in haswell_set_pipeconf()
8766 		I915_WRITE(PIPEMISC(pipe), val);  in haswell_set_pipeconf()
9397 		I915_WRITE(D_COMP_BDW, val);  in hsw_write_dcomp()
9421 		I915_WRITE(LCPLL_CTL, val);  in hsw_disable_lcpll()
9431 	I915_WRITE(LCPLL_CTL, val);  in hsw_disable_lcpll()
9449 		I915_WRITE(LCPLL_CTL, val);  in hsw_disable_lcpll()
9476 		I915_WRITE(LCPLL_CTL, val);  in hsw_restore_lcpll()
9487 	I915_WRITE(LCPLL_CTL, val);  in hsw_restore_lcpll()
9495 		I915_WRITE(LCPLL_CTL, val);  in hsw_restore_lcpll()
9539 		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);  in hsw_enable_pc8()
9559 		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);  in hsw_disable_pc8()
9627 	I915_WRITE(LCPLL_CTL, val);  in broadwell_set_cdclk()
9658 	I915_WRITE(LCPLL_CTL, val);  in broadwell_set_cdclk()
9662 	I915_WRITE(LCPLL_CTL, val);  in broadwell_set_cdclk()
9968 		I915_WRITE(CURCNTR(PIPE_A), 0);  in i845_update_cursor()
9974 		I915_WRITE(CURBASE(PIPE_A), base);  in i845_update_cursor()
9979 		I915_WRITE(CURSIZE, size);  in i845_update_cursor()
9984 		I915_WRITE(CURCNTR(PIPE_A), cntl);  in i845_update_cursor()
10024 		I915_WRITE(CURCNTR(pipe), cntl);  in i9xx_update_cursor()
10030 	I915_WRITE(CURBASE(pipe), base);  in i9xx_update_cursor()
10075 	I915_WRITE(CURPOS(pipe), pos);  in intel_crtc_update_cursor()
11220 	I915_WRITE(PLANE_CTL(pipe, 0), ctl);  in skl_do_mmio_flip()
11221 	I915_WRITE(PLANE_STRIDE(pipe, 0), stride);  in skl_do_mmio_flip()
11223 	I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);  in skl_do_mmio_flip()
11246 	I915_WRITE(reg, dspcntr);  in ilk_do_mmio_flip()
11248 	I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);  in ilk_do_mmio_flip()
13358 	I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);  in ibx_pch_dpll_mode_set()
13359 	I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);  in ibx_pch_dpll_mode_set()
13368 	I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);  in ibx_pch_dpll_enable()
13379 	I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);  in ibx_pch_dpll_enable()
13396 	I915_WRITE(PCH_DPLL(pll->id), 0);  in ibx_pch_dpll_disable()
14862 	I915_WRITE(vga_reg, VGA_DISP_DISABLE);  in i915_disable_vga()
15061 	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);  in intel_sanitize_crtc()