1291 	enum pipe panel_pipe = PIPE_A;  in assert_panel_unlocked()
1334 		cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;  in assert_cursor()
1353 	if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||  in assert_pipe()
1775 		I915_WRITE(DPLL(PIPE_A),  in i9xx_disable_pll()
1776 			   I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);  in i9xx_disable_pll()
1780 	if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||  in i9xx_disable_pll()
1821 	if (pipe != PIPE_A)  in chv_disable_pll()
2033 	val = I915_READ(TRANS_CHICKEN2(PIPE_A));  in lpt_enable_pch_transcoder()
2035 	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);  in lpt_enable_pch_transcoder()
2093 	val = I915_READ(TRANS_CHICKEN2(PIPE_A));  in lpt_disable_pch_transcoder()
2095 	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);  in lpt_disable_pch_transcoder()
2150 		WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||  in intel_enable_pipe()
2200 	if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&  in intel_disable_pipe()
4120 	case PIPE_A:  in ivybridge_update_fdi_bc_bifurcation()
4245 	ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);  in lpt_pch_enable()
4963 	return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;  in hsw_crtc_supports_ips()
6525 	case PIPE_A:  in ironlake_check_fdi_lanes()
6663 		if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&  in intel_crtc_compute_config()
7389 		if (pipe == PIPE_A)  in vlv_prepare_pll()
7397 		if (pipe == PIPE_A)  in vlv_prepare_pll()
7422 	if (crtc->pipe != PIPE_A)  in chv_compute_dpll()
7838 	if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||  in i9xx_set_pipeconf()
9839 		tmp = I915_READ(FDI_RX_CTL(PIPE_A));  in haswell_get_ddi_port_state()
9870 			trans_edp_pipe = PIPE_A;  in haswell_get_pipe_config()
9968 		I915_WRITE(CURCNTR(PIPE_A), 0);  in i845_update_cursor()
9969 		POSTING_READ(CURCNTR(PIPE_A));  in i845_update_cursor()
9974 		I915_WRITE(CURBASE(PIPE_A), base);  in i845_update_cursor()
9984 		I915_WRITE(CURCNTR(PIPE_A), cntl);  in i845_update_cursor()
9985 		POSTING_READ(CURCNTR(PIPE_A));  in i845_update_cursor()
12778 		if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||  in check_crtc_state()
15099 	    crtc->pipe == PIPE_A && !crtc->active) {  in intel_sanitize_crtc()