Lines Matching refs:crtc
86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
107 static void chv_prepare_pll(struct intel_crtc *crtc,
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
119 static void intel_pre_disable_primary(struct drm_crtc *crtc);
510 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) in intel_pipe_has_type() argument
512 struct drm_device *dev = crtc->base.dev; in intel_pipe_has_type()
515 for_each_encoder_on_crtc(dev, &crtc->base, encoder) in intel_pipe_has_type()
538 if (connector_state->crtc != crtc_state->base.crtc) in intel_pipe_will_have_type()
556 struct drm_device *dev = crtc_state->base.crtc->dev; in intel_ironlake_limit()
580 struct drm_device *dev = crtc_state->base.crtc->dev; in intel_g4x_limit()
602 struct drm_device *dev = crtc_state->base.crtc->dev; in intel_limit()
745 struct drm_device *dev = crtc_state->base.crtc->dev; in i9xx_select_p2_div()
771 struct drm_device *dev = crtc_state->base.crtc->dev; in i9xx_find_best_dpll()
818 struct drm_device *dev = crtc_state->base.crtc->dev; in pnv_find_best_dpll()
863 struct drm_device *dev = crtc_state->base.crtc->dev; in g4x_find_best_dpll()
951 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in vlv_find_best_dpll() local
952 struct drm_device *dev = crtc->base.dev; in vlv_find_best_dpll()
1005 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in chv_find_best_dpll() local
1006 struct drm_device *dev = crtc->base.dev; in chv_find_best_dpll()
1066 bool intel_crtc_active(struct drm_crtc *crtc) in intel_crtc_active() argument
1068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_active()
1083 return intel_crtc->active && crtc->primary->state->fb && in intel_crtc_active()
1090 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_pipe_to_cpu_transcoder() local
1091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_pipe_to_cpu_transcoder()
1131 static void intel_wait_for_pipe_off(struct intel_crtc *crtc) in intel_wait_for_pipe_off() argument
1133 struct drm_device *dev = crtc->base.dev; in intel_wait_for_pipe_off()
1135 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; in intel_wait_for_pipe_off()
1136 enum pipe pipe = crtc->pipe; in intel_wait_for_pipe_off()
1190 intel_crtc_to_shared_dpll(struct intel_crtc *crtc) in intel_crtc_to_shared_dpll() argument
1192 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; in intel_crtc_to_shared_dpll()
1194 if (crtc->config->shared_dpll < 0) in intel_crtc_to_shared_dpll()
1197 return &dev_priv->shared_dplls[crtc->config->shared_dpll]; in intel_crtc_to_shared_dpll()
1445 static void assert_vblank_disabled(struct drm_crtc *crtc) in assert_vblank_disabled() argument
1447 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) in assert_vblank_disabled()
1448 drm_crtc_vblank_put(crtc); in assert_vblank_disabled()
1598 static void vlv_enable_pll(struct intel_crtc *crtc, in vlv_enable_pll() argument
1601 struct drm_device *dev = crtc->base.dev; in vlv_enable_pll()
1603 int reg = DPLL(crtc->pipe); in vlv_enable_pll()
1606 assert_pipe_disabled(dev_priv, crtc->pipe); in vlv_enable_pll()
1613 assert_panel_unlocked(dev_priv, crtc->pipe); in vlv_enable_pll()
1620 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); in vlv_enable_pll()
1622 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1623 POSTING_READ(DPLL_MD(crtc->pipe)); in vlv_enable_pll()
1637 static void chv_enable_pll(struct intel_crtc *crtc, in chv_enable_pll() argument
1640 struct drm_device *dev = crtc->base.dev; in chv_enable_pll()
1642 int pipe = crtc->pipe; in chv_enable_pll()
1646 assert_pipe_disabled(dev_priv, crtc->pipe); in chv_enable_pll()
1678 struct intel_crtc *crtc; in intel_num_dvo_pipes() local
1681 for_each_intel_crtc(dev, crtc) in intel_num_dvo_pipes()
1682 count += crtc->base.state->active && in intel_num_dvo_pipes()
1683 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); in intel_num_dvo_pipes()
1688 static void i9xx_enable_pll(struct intel_crtc *crtc) in i9xx_enable_pll() argument
1690 struct drm_device *dev = crtc->base.dev; in i9xx_enable_pll()
1692 int reg = DPLL(crtc->pipe); in i9xx_enable_pll()
1693 u32 dpll = crtc->config->dpll_hw_state.dpll; in i9xx_enable_pll()
1695 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_enable_pll()
1702 assert_panel_unlocked(dev_priv, crtc->pipe); in i9xx_enable_pll()
1713 I915_WRITE(DPLL(!crtc->pipe), in i9xx_enable_pll()
1714 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); in i9xx_enable_pll()
1731 I915_WRITE(DPLL_MD(crtc->pipe), in i9xx_enable_pll()
1732 crtc->config->dpll_hw_state.dpll_md); in i9xx_enable_pll()
1763 static void i9xx_disable_pll(struct intel_crtc *crtc) in i9xx_disable_pll() argument
1765 struct drm_device *dev = crtc->base.dev; in i9xx_disable_pll()
1767 enum pipe pipe = crtc->pipe; in i9xx_disable_pll()
1771 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && in i9xx_disable_pll()
1866 static void intel_prepare_shared_dpll(struct intel_crtc *crtc) in intel_prepare_shared_dpll() argument
1868 struct drm_device *dev = crtc->base.dev; in intel_prepare_shared_dpll()
1870 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); in intel_prepare_shared_dpll()
1893 static void intel_enable_shared_dpll(struct intel_crtc *crtc) in intel_enable_shared_dpll() argument
1895 struct drm_device *dev = crtc->base.dev; in intel_enable_shared_dpll()
1897 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); in intel_enable_shared_dpll()
1907 crtc->base.base.id); in intel_enable_shared_dpll()
1923 static void intel_disable_shared_dpll(struct intel_crtc *crtc) in intel_disable_shared_dpll() argument
1925 struct drm_device *dev = crtc->base.dev; in intel_disable_shared_dpll()
1927 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); in intel_disable_shared_dpll()
1936 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) in intel_disable_shared_dpll()
1941 crtc->base.base.id); in intel_disable_shared_dpll()
1964 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in ironlake_enable_pch_transcoder() local
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_enable_pch_transcoder()
2105 static void intel_enable_pipe(struct intel_crtc *crtc) in intel_enable_pipe() argument
2107 struct drm_device *dev = crtc->base.dev; in intel_enable_pipe()
2109 enum pipe pipe = crtc->pipe; in intel_enable_pipe()
2133 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) in intel_enable_pipe()
2138 if (crtc->config->has_pch_encoder) { in intel_enable_pipe()
2169 static void intel_disable_pipe(struct intel_crtc *crtc) in intel_disable_pipe() argument
2171 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; in intel_disable_pipe()
2172 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; in intel_disable_pipe()
2173 enum pipe pipe = crtc->pipe; in intel_disable_pipe()
2196 if (crtc->config->double_wide) in intel_disable_pipe()
2206 intel_wait_for_pipe_off(crtc); in intel_disable_pipe()
2528 intel_alloc_initial_plane_obj(struct intel_crtc *crtc, in intel_alloc_initial_plane_obj() argument
2531 struct drm_device *dev = crtc->base.dev; in intel_alloc_initial_plane_obj()
2680 primary->crtc = primary->state->crtc = &intel_crtc->base; in intel_find_initial_plane_obj()
2685 static void i9xx_update_primary_plane(struct drm_crtc *crtc, in i9xx_update_primary_plane() argument
2689 struct drm_device *dev = crtc->dev; in i9xx_update_primary_plane()
2691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_update_primary_plane()
2692 struct drm_plane *primary = crtc->primary; in i9xx_update_primary_plane()
2786 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { in i9xx_update_primary_plane()
2815 static void ironlake_update_primary_plane(struct drm_crtc *crtc, in ironlake_update_primary_plane() argument
2819 struct drm_device *dev = crtc->dev; in ironlake_update_primary_plane()
2821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_update_primary_plane()
2822 struct drm_plane *primary = crtc->primary; in ironlake_update_primary_plane()
2887 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { in ironlake_update_primary_plane()
3087 static void skylake_update_primary_plane(struct drm_crtc *crtc, in skylake_update_primary_plane() argument
3091 struct drm_device *dev = crtc->dev; in skylake_update_primary_plane()
3093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in skylake_update_primary_plane()
3094 struct drm_plane *plane = crtc->primary; in skylake_update_primary_plane()
3194 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, in intel_pipe_set_base_atomic() argument
3197 struct drm_device *dev = crtc->dev; in intel_pipe_set_base_atomic()
3203 dev_priv->display.update_primary_plane(crtc, fb, x, y); in intel_pipe_set_base_atomic()
3210 struct drm_crtc *crtc; in intel_complete_page_flips() local
3212 for_each_crtc(dev, crtc) { in intel_complete_page_flips()
3213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_complete_page_flips()
3223 struct drm_crtc *crtc; in intel_update_primary_planes() local
3225 for_each_crtc(dev, crtc) { in intel_update_primary_planes()
3226 struct intel_plane *plane = to_intel_plane(crtc->primary); in intel_update_primary_planes()
3229 drm_modeset_lock_crtc(crtc, &plane->base); in intel_update_primary_planes()
3236 drm_modeset_unlock_crtc(crtc); in intel_update_primary_planes()
3335 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) in intel_crtc_has_pending_flip() argument
3337 struct drm_device *dev = crtc->dev; in intel_crtc_has_pending_flip()
3339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_has_pending_flip()
3347 pending = to_intel_crtc(crtc)->unpin_work != NULL; in intel_crtc_has_pending_flip()
3353 static void intel_update_pipe_config(struct intel_crtc *crtc, in intel_update_pipe_config() argument
3356 struct drm_device *dev = crtc->base.dev; in intel_update_pipe_config()
3359 to_intel_crtc_state(crtc->base.state); in intel_update_pipe_config()
3362 crtc->base.mode = crtc->base.state->mode; in intel_update_pipe_config()
3369 intel_set_pipe_csc(&crtc->base); in intel_update_pipe_config()
3380 I915_WRITE(PIPESRC(crtc->pipe), in intel_update_pipe_config()
3386 skl_detach_scalers(crtc); in intel_update_pipe_config()
3389 skylake_pfit_enable(crtc); in intel_update_pipe_config()
3392 ironlake_pfit_enable(crtc); in intel_update_pipe_config()
3394 ironlake_pfit_disable(crtc, true); in intel_update_pipe_config()
3398 static void intel_fdi_normal_train(struct drm_crtc *crtc) in intel_fdi_normal_train() argument
3400 struct drm_device *dev = crtc->dev; in intel_fdi_normal_train()
3402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_fdi_normal_train()
3440 static void ironlake_fdi_link_train(struct drm_crtc *crtc) in ironlake_fdi_link_train() argument
3442 struct drm_device *dev = crtc->dev; in ironlake_fdi_link_train()
3444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_fdi_link_train()
3540 static void gen6_fdi_link_train(struct drm_crtc *crtc) in gen6_fdi_link_train() argument
3542 struct drm_device *dev = crtc->dev; in gen6_fdi_link_train()
3544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in gen6_fdi_link_train()
3672 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) in ivb_manual_fdi_link_train() argument
3674 struct drm_device *dev = crtc->dev; in ivb_manual_fdi_link_train()
3676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ivb_manual_fdi_link_train()
3856 static void ironlake_fdi_disable(struct drm_crtc *crtc) in ironlake_fdi_disable() argument
3858 struct drm_device *dev = crtc->dev; in ironlake_fdi_disable()
3860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_fdi_disable()
3910 struct intel_crtc *crtc; in intel_has_pending_fb_unpin() local
3919 for_each_intel_crtc(dev, crtc) { in intel_has_pending_fb_unpin()
3920 if (atomic_read(&crtc->unpin_work_count) == 0) in intel_has_pending_fb_unpin()
3923 if (crtc->unpin_work) in intel_has_pending_fb_unpin()
3924 intel_wait_for_vblank(dev, crtc->pipe); in intel_has_pending_fb_unpin()
3955 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) in intel_crtc_wait_for_pending_flips() argument
3957 struct drm_device *dev = crtc->dev; in intel_crtc_wait_for_pending_flips()
3962 !intel_crtc_has_pending_flip(crtc), in intel_crtc_wait_for_pending_flips()
3964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_wait_for_pending_flips()
3974 if (crtc->primary->fb) { in intel_crtc_wait_for_pending_flips()
3976 intel_finish_fb(crtc->primary->fb); in intel_crtc_wait_for_pending_flips()
3982 static void lpt_program_iclkip(struct drm_crtc *crtc) in lpt_program_iclkip() argument
3984 struct drm_device *dev = crtc->dev; in lpt_program_iclkip()
3986 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; in lpt_program_iclkip()
4070 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, in ironlake_pch_transcoder_set_timings() argument
4073 struct drm_device *dev = crtc->base.dev; in ironlake_pch_transcoder_set_timings()
4075 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; in ironlake_pch_transcoder_set_timings()
4146 static void ironlake_pch_enable(struct drm_crtc *crtc) in ironlake_pch_enable() argument
4148 struct drm_device *dev = crtc->dev; in ironlake_pch_enable()
4150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_pch_enable()
4165 dev_priv->display.fdi_link_train(crtc); in ironlake_pch_enable()
4195 intel_fdi_normal_train(crtc); in ironlake_pch_enable()
4208 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) in ironlake_pch_enable()
4210 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) in ironlake_pch_enable()
4213 switch (intel_trans_dp_port_sel(crtc)) { in ironlake_pch_enable()
4233 static void lpt_pch_enable(struct drm_crtc *crtc) in lpt_pch_enable() argument
4235 struct drm_device *dev = crtc->dev; in lpt_pch_enable()
4237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in lpt_pch_enable()
4242 lpt_program_iclkip(crtc); in lpt_pch_enable()
4250 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, in intel_get_shared_dpll() argument
4253 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; in intel_get_shared_dpll()
4263 i = (enum intel_dpll_id) crtc->pipe; in intel_get_shared_dpll()
4267 crtc->base.base.id, pll->name); in intel_get_shared_dpll()
4288 crtc->base.base.id, pll->name); in intel_get_shared_dpll()
4307 crtc->base.base.id, pll->name, in intel_get_shared_dpll()
4319 crtc->base.base.id, pll->name); in intel_get_shared_dpll()
4333 pipe_name(crtc->pipe)); in intel_get_shared_dpll()
4335 shared_dpll[i].crtc_mask |= 1 << crtc->pipe; in intel_get_shared_dpll()
4379 to_intel_crtc(crtc_state->base.crtc); in skl_update_scaler()
4443 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); in skl_update_scaler_crtc()
4469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); in skl_update_scaler_plane()
4523 static void skylake_scaler_disable(struct intel_crtc *crtc) in skylake_scaler_disable() argument
4527 for (i = 0; i < crtc->num_scalers; i++) in skylake_scaler_disable()
4528 skl_detach_scaler(crtc, i); in skylake_scaler_disable()
4531 static void skylake_pfit_enable(struct intel_crtc *crtc) in skylake_pfit_enable() argument
4533 struct drm_device *dev = crtc->base.dev; in skylake_pfit_enable()
4535 int pipe = crtc->pipe; in skylake_pfit_enable()
4537 &crtc->config->scaler_state; in skylake_pfit_enable()
4539 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); in skylake_pfit_enable()
4541 if (crtc->config->pch_pfit.enabled) { in skylake_pfit_enable()
4544 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { in skylake_pfit_enable()
4552 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); in skylake_pfit_enable()
4553 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); in skylake_pfit_enable()
4555 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); in skylake_pfit_enable()
4559 static void ironlake_pfit_enable(struct intel_crtc *crtc) in ironlake_pfit_enable() argument
4561 struct drm_device *dev = crtc->base.dev; in ironlake_pfit_enable()
4563 int pipe = crtc->pipe; in ironlake_pfit_enable()
4565 if (crtc->config->pch_pfit.enabled) { in ironlake_pfit_enable()
4575 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); in ironlake_pfit_enable()
4576 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); in ironlake_pfit_enable()
4580 void hsw_enable_ips(struct intel_crtc *crtc) in hsw_enable_ips() argument
4582 struct drm_device *dev = crtc->base.dev; in hsw_enable_ips()
4585 if (!crtc->config->ips_enabled) in hsw_enable_ips()
4589 intel_wait_for_vblank(dev, crtc->pipe); in hsw_enable_ips()
4591 assert_plane_enabled(dev_priv, crtc->plane); in hsw_enable_ips()
4613 void hsw_disable_ips(struct intel_crtc *crtc) in hsw_disable_ips() argument
4615 struct drm_device *dev = crtc->base.dev; in hsw_disable_ips()
4618 if (!crtc->config->ips_enabled) in hsw_disable_ips()
4621 assert_plane_enabled(dev_priv, crtc->plane); in hsw_disable_ips()
4635 intel_wait_for_vblank(dev, crtc->pipe); in hsw_disable_ips()
4639 static void intel_crtc_load_lut(struct drm_crtc *crtc) in intel_crtc_load_lut() argument
4641 struct drm_device *dev = crtc->dev; in intel_crtc_load_lut()
4643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_load_lut()
4649 if (!crtc->state->active) in intel_crtc_load_lut()
4716 intel_post_enable_primary(struct drm_crtc *crtc) in intel_post_enable_primary() argument
4718 struct drm_device *dev = crtc->dev; in intel_post_enable_primary()
4720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_post_enable_primary()
4765 intel_pre_disable_primary(struct drm_crtc *crtc) in intel_pre_disable_primary() argument
4767 struct drm_device *dev = crtc->dev; in intel_pre_disable_primary()
4769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_pre_disable_primary()
4805 static void intel_post_plane_update(struct intel_crtc *crtc) in intel_post_plane_update() argument
4807 struct intel_crtc_atomic_commit *atomic = &crtc->atomic; in intel_post_plane_update()
4808 struct drm_device *dev = crtc->base.dev; in intel_post_plane_update()
4813 intel_wait_for_vblank(dev, crtc->pipe); in intel_post_plane_update()
4818 crtc->wm.cxsr_allowed = true; in intel_post_plane_update()
4820 if (crtc->atomic.update_wm_post) in intel_post_plane_update()
4821 intel_update_watermarks(&crtc->base); in intel_post_plane_update()
4827 intel_post_enable_primary(&crtc->base); in intel_post_plane_update()
4830 intel_update_sprite_watermarks(plane, &crtc->base, in intel_post_plane_update()
4836 static void intel_pre_plane_update(struct intel_crtc *crtc) in intel_pre_plane_update() argument
4838 struct drm_device *dev = crtc->base.dev; in intel_pre_plane_update()
4840 struct intel_crtc_atomic_commit *atomic = &crtc->atomic; in intel_pre_plane_update()
4854 intel_crtc_wait_for_pending_flips(&crtc->base); in intel_pre_plane_update()
4857 intel_fbc_disable_crtc(crtc); in intel_pre_plane_update()
4859 if (crtc->atomic.disable_ips) in intel_pre_plane_update()
4860 hsw_disable_ips(crtc); in intel_pre_plane_update()
4863 intel_pre_disable_primary(&crtc->base); in intel_pre_plane_update()
4866 crtc->wm.cxsr_allowed = false; in intel_pre_plane_update()
4871 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) in intel_crtc_disable_planes() argument
4873 struct drm_device *dev = crtc->dev; in intel_crtc_disable_planes()
4874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_disable_planes()
4881 to_intel_plane(p)->disable_plane(p, crtc); in intel_crtc_disable_planes()
4891 static void ironlake_crtc_enable(struct drm_crtc *crtc) in ironlake_crtc_enable() argument
4893 struct drm_device *dev = crtc->dev; in ironlake_crtc_enable()
4895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_crtc_enable()
4915 ironlake_set_pipeconf(crtc); in ironlake_crtc_enable()
4922 for_each_encoder_on_crtc(dev, crtc, encoder) in ironlake_crtc_enable()
4942 intel_crtc_load_lut(crtc); in ironlake_crtc_enable()
4944 intel_update_watermarks(crtc); in ironlake_crtc_enable()
4948 ironlake_pch_enable(crtc); in ironlake_crtc_enable()
4950 assert_vblank_disabled(crtc); in ironlake_crtc_enable()
4951 drm_crtc_vblank_on(crtc); in ironlake_crtc_enable()
4953 for_each_encoder_on_crtc(dev, crtc, encoder) in ironlake_crtc_enable()
4961 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) in hsw_crtc_supports_ips() argument
4963 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; in hsw_crtc_supports_ips()
4966 static void haswell_crtc_enable(struct drm_crtc *crtc) in haswell_crtc_enable() argument
4968 struct drm_device *dev = crtc->dev; in haswell_crtc_enable()
4970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in haswell_crtc_enable()
4974 to_intel_crtc_state(crtc->state); in haswell_crtc_enable()
4998 haswell_set_pipeconf(crtc); in haswell_crtc_enable()
5000 intel_set_pipe_csc(crtc); in haswell_crtc_enable()
5005 for_each_encoder_on_crtc(dev, crtc, encoder) { in haswell_crtc_enable()
5015 dev_priv->display.fdi_link_train(crtc); in haswell_crtc_enable()
5030 intel_crtc_load_lut(crtc); in haswell_crtc_enable()
5032 intel_ddi_set_pipe_settings(crtc); in haswell_crtc_enable()
5034 intel_ddi_enable_transcoder_func(crtc); in haswell_crtc_enable()
5036 intel_update_watermarks(crtc); in haswell_crtc_enable()
5040 lpt_pch_enable(crtc); in haswell_crtc_enable()
5043 intel_ddi_set_vc_payload_alloc(crtc, true); in haswell_crtc_enable()
5045 assert_vblank_disabled(crtc); in haswell_crtc_enable()
5046 drm_crtc_vblank_on(crtc); in haswell_crtc_enable()
5048 for_each_encoder_on_crtc(dev, crtc, encoder) { in haswell_crtc_enable()
5062 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) in ironlake_pfit_disable() argument
5064 struct drm_device *dev = crtc->base.dev; in ironlake_pfit_disable()
5066 int pipe = crtc->pipe; in ironlake_pfit_disable()
5070 if (force || crtc->config->pch_pfit.enabled) { in ironlake_pfit_disable()
5077 static void ironlake_crtc_disable(struct drm_crtc *crtc) in ironlake_crtc_disable() argument
5079 struct drm_device *dev = crtc->dev; in ironlake_crtc_disable()
5081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_crtc_disable()
5086 for_each_encoder_on_crtc(dev, crtc, encoder) in ironlake_crtc_disable()
5089 drm_crtc_vblank_off(crtc); in ironlake_crtc_disable()
5090 assert_vblank_disabled(crtc); in ironlake_crtc_disable()
5100 ironlake_fdi_disable(crtc); in ironlake_crtc_disable()
5102 for_each_encoder_on_crtc(dev, crtc, encoder) in ironlake_crtc_disable()
5128 static void haswell_crtc_disable(struct drm_crtc *crtc) in haswell_crtc_disable() argument
5130 struct drm_device *dev = crtc->dev; in haswell_crtc_disable()
5132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in haswell_crtc_disable()
5137 for_each_encoder_on_crtc(dev, crtc, encoder) { in haswell_crtc_disable()
5142 drm_crtc_vblank_off(crtc); in haswell_crtc_disable()
5143 assert_vblank_disabled(crtc); in haswell_crtc_disable()
5151 intel_ddi_set_vc_payload_alloc(crtc, false); in haswell_crtc_disable()
5166 intel_ddi_fdi_disable(crtc); in haswell_crtc_disable()
5169 for_each_encoder_on_crtc(dev, crtc, encoder) in haswell_crtc_disable()
5174 static void i9xx_pfit_enable(struct intel_crtc *crtc) in i9xx_pfit_enable() argument
5176 struct drm_device *dev = crtc->base.dev; in i9xx_pfit_enable()
5178 struct intel_crtc_state *pipe_config = crtc->config; in i9xx_pfit_enable()
5188 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_pfit_enable()
5195 I915_WRITE(BCLRPAT(crtc->pipe), 0); in i9xx_pfit_enable()
5298 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) in get_crtc_power_domains() argument
5300 struct drm_device *dev = crtc->dev; in get_crtc_power_domains()
5302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in get_crtc_power_domains()
5307 if (!crtc->state->active) in get_crtc_power_domains()
5318 for_each_encoder_on_crtc(dev, crtc, intel_encoder) in get_crtc_power_domains()
5324 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) in modeset_get_crtc_power_domains() argument
5326 struct drm_i915_private *dev_priv = crtc->dev->dev_private; in modeset_get_crtc_power_domains()
5327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in modeset_get_crtc_power_domains()
5332 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); in modeset_get_crtc_power_domains()
5357 struct drm_crtc *crtc; in modeset_update_crtc_power_domains() local
5360 for_each_crtc_in_state(state, crtc, crtc_state, i) { in modeset_update_crtc_power_domains()
5361 if (needs_modeset(crtc->state)) in modeset_update_crtc_power_domains()
5362 put_domains[to_intel_crtc(crtc)->pipe] = in modeset_update_crtc_power_domains()
5363 modeset_get_crtc_power_domains(crtc); in modeset_update_crtc_power_domains()
6135 static void valleyview_crtc_enable(struct drm_crtc *crtc) in valleyview_crtc_enable() argument
6137 struct drm_device *dev = crtc->dev; in valleyview_crtc_enable()
6139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in valleyview_crtc_enable()
6167 for_each_encoder_on_crtc(dev, crtc, encoder) in valleyview_crtc_enable()
6181 for_each_encoder_on_crtc(dev, crtc, encoder) in valleyview_crtc_enable()
6187 intel_crtc_load_lut(crtc); in valleyview_crtc_enable()
6191 assert_vblank_disabled(crtc); in valleyview_crtc_enable()
6192 drm_crtc_vblank_on(crtc); in valleyview_crtc_enable()
6194 for_each_encoder_on_crtc(dev, crtc, encoder) in valleyview_crtc_enable()
6198 static void i9xx_set_pll_dividers(struct intel_crtc *crtc) in i9xx_set_pll_dividers() argument
6200 struct drm_device *dev = crtc->base.dev; in i9xx_set_pll_dividers()
6203 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); in i9xx_set_pll_dividers()
6204 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); in i9xx_set_pll_dividers()
6207 static void i9xx_crtc_enable(struct drm_crtc *crtc) in i9xx_crtc_enable() argument
6209 struct drm_device *dev = crtc->dev; in i9xx_crtc_enable()
6211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_crtc_enable()
6232 for_each_encoder_on_crtc(dev, crtc, encoder) in i9xx_crtc_enable()
6240 intel_crtc_load_lut(crtc); in i9xx_crtc_enable()
6242 intel_update_watermarks(crtc); in i9xx_crtc_enable()
6245 assert_vblank_disabled(crtc); in i9xx_crtc_enable()
6246 drm_crtc_vblank_on(crtc); in i9xx_crtc_enable()
6248 for_each_encoder_on_crtc(dev, crtc, encoder) in i9xx_crtc_enable()
6252 static void i9xx_pfit_disable(struct intel_crtc *crtc) in i9xx_pfit_disable() argument
6254 struct drm_device *dev = crtc->base.dev; in i9xx_pfit_disable()
6257 if (!crtc->config->gmch_pfit.control) in i9xx_pfit_disable()
6260 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_pfit_disable()
6267 static void i9xx_crtc_disable(struct drm_crtc *crtc) in i9xx_crtc_disable() argument
6269 struct drm_device *dev = crtc->dev; in i9xx_crtc_disable()
6271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_crtc_disable()
6283 for_each_encoder_on_crtc(dev, crtc, encoder) in i9xx_crtc_disable()
6286 drm_crtc_vblank_off(crtc); in i9xx_crtc_disable()
6287 assert_vblank_disabled(crtc); in i9xx_crtc_disable()
6293 for_each_encoder_on_crtc(dev, crtc, encoder) in i9xx_crtc_disable()
6306 for_each_encoder_on_crtc(dev, crtc, encoder) in i9xx_crtc_disable()
6314 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) in intel_crtc_disable_noatomic() argument
6316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_disable_noatomic()
6317 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in intel_crtc_disable_noatomic()
6324 if (to_intel_plane_state(crtc->primary->state)->visible) { in intel_crtc_disable_noatomic()
6325 intel_crtc_wait_for_pending_flips(crtc); in intel_crtc_disable_noatomic()
6326 intel_pre_disable_primary(crtc); in intel_crtc_disable_noatomic()
6328 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); in intel_crtc_disable_noatomic()
6329 to_intel_plane_state(crtc->primary->state)->visible = false; in intel_crtc_disable_noatomic()
6332 dev_priv->display.crtc_disable(crtc); in intel_crtc_disable_noatomic()
6334 intel_update_watermarks(crtc); in intel_crtc_disable_noatomic()
6352 struct drm_crtc *crtc; in intel_display_suspend() local
6367 for_each_crtc(dev, crtc) { in intel_display_suspend()
6369 drm_atomic_get_crtc_state(state, crtc); in intel_display_suspend()
6379 crtc_mask |= 1 << drm_crtc_index(crtc); in intel_display_suspend()
6386 for_each_crtc(dev, crtc) in intel_display_suspend()
6387 if (crtc_mask & (1 << drm_crtc_index(crtc))) in intel_display_suspend()
6388 crtc->state->active = true; in intel_display_suspend()
6413 struct drm_crtc *crtc = connector->base.state->crtc; in intel_connector_check_state() local
6423 I915_STATE_WARN(!crtc, in intel_connector_check_state()
6426 if (!crtc) in intel_connector_check_state()
6429 I915_STATE_WARN(!crtc->state->active, in intel_connector_check_state()
6438 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, in intel_connector_check_state()
6441 I915_STATE_WARN(crtc && crtc->state->active, in intel_connector_check_state()
6443 I915_STATE_WARN(!crtc && connector->base.state->best_encoder, in intel_connector_check_state()
6634 static void hsw_compute_ips_config(struct intel_crtc *crtc, in hsw_compute_ips_config() argument
6637 struct drm_device *dev = crtc->base.dev; in hsw_compute_ips_config()
6641 hsw_crtc_supports_ips(crtc) && in hsw_compute_ips_config()
6645 static int intel_crtc_compute_config(struct intel_crtc *crtc, in intel_crtc_compute_config() argument
6648 struct drm_device *dev = crtc->base.dev; in intel_crtc_compute_config()
6663 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && in intel_crtc_compute_config()
6691 hsw_compute_ips_config(crtc, pipe_config); in intel_crtc_compute_config()
6694 return ironlake_fdi_compute_config(crtc, pipe_config); in intel_crtc_compute_config()
7141 struct drm_device *dev = crtc_state->base.crtc->dev; in i9xx_get_refclk()
7172 static void i9xx_update_pll_dividers(struct intel_crtc *crtc, in i9xx_update_pll_dividers() argument
7176 struct drm_device *dev = crtc->base.dev; in i9xx_update_pll_dividers()
7191 crtc->lowfreq_avail = false; in i9xx_update_pll_dividers()
7195 crtc->lowfreq_avail = true; in i9xx_update_pll_dividers()
7230 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, in intel_pch_transcoder_set_m_n() argument
7233 struct drm_device *dev = crtc->base.dev; in intel_pch_transcoder_set_m_n()
7235 int pipe = crtc->pipe; in intel_pch_transcoder_set_m_n()
7243 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, in intel_cpu_transcoder_set_m_n() argument
7247 struct drm_device *dev = crtc->base.dev; in intel_cpu_transcoder_set_m_n()
7249 int pipe = crtc->pipe; in intel_cpu_transcoder_set_m_n()
7250 enum transcoder transcoder = crtc->config->cpu_transcoder; in intel_cpu_transcoder_set_m_n()
7262 crtc->config->has_drrs) { in intel_cpu_transcoder_set_m_n()
7277 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) in intel_dp_set_m_n() argument
7282 dp_m_n = &crtc->config->dp_m_n; in intel_dp_set_m_n()
7283 dp_m2_n2 = &crtc->config->dp_m2_n2; in intel_dp_set_m_n()
7290 dp_m_n = &crtc->config->dp_m2_n2; in intel_dp_set_m_n()
7296 if (crtc->config->has_pch_encoder) in intel_dp_set_m_n()
7297 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); in intel_dp_set_m_n()
7299 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); in intel_dp_set_m_n()
7302 static void vlv_compute_dpll(struct intel_crtc *crtc, in vlv_compute_dpll() argument
7315 if (crtc->pipe == PIPE_B) in vlv_compute_dpll()
7325 static void vlv_prepare_pll(struct intel_crtc *crtc, in vlv_prepare_pll() argument
7328 struct drm_device *dev = crtc->base.dev; in vlv_prepare_pll()
7330 int pipe = crtc->pipe; in vlv_prepare_pll()
7379 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || in vlv_prepare_pll()
7380 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) in vlv_prepare_pll()
7407 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || in vlv_prepare_pll()
7408 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) in vlv_prepare_pll()
7416 static void chv_compute_dpll(struct intel_crtc *crtc, in chv_compute_dpll() argument
7422 if (crtc->pipe != PIPE_A) in chv_compute_dpll()
7429 static void chv_prepare_pll(struct intel_crtc *crtc, in chv_prepare_pll() argument
7432 struct drm_device *dev = crtc->base.dev; in chv_prepare_pll()
7434 int pipe = crtc->pipe; in chv_prepare_pll()
7435 int dpll_reg = DPLL(crtc->pipe); in chv_prepare_pll()
7546 struct intel_crtc *crtc = in vlv_force_pll_on() local
7549 .base.crtc = &crtc->base, in vlv_force_pll_on()
7555 chv_compute_dpll(crtc, &pipe_config); in vlv_force_pll_on()
7556 chv_prepare_pll(crtc, &pipe_config); in vlv_force_pll_on()
7557 chv_enable_pll(crtc, &pipe_config); in vlv_force_pll_on()
7559 vlv_compute_dpll(crtc, &pipe_config); in vlv_force_pll_on()
7560 vlv_prepare_pll(crtc, &pipe_config); in vlv_force_pll_on()
7561 vlv_enable_pll(crtc, &pipe_config); in vlv_force_pll_on()
7581 static void i9xx_compute_dpll(struct intel_crtc *crtc, in i9xx_compute_dpll() argument
7586 struct drm_device *dev = crtc->base.dev; in i9xx_compute_dpll()
7592 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); in i9xx_compute_dpll()
7658 static void i8xx_compute_dpll(struct intel_crtc *crtc, in i8xx_compute_dpll() argument
7663 struct drm_device *dev = crtc->base.dev; in i8xx_compute_dpll()
7668 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); in i8xx_compute_dpll()
7764 static void intel_get_pipe_timings(struct intel_crtc *crtc, in intel_get_pipe_timings() argument
7767 struct drm_device *dev = crtc->base.dev; in intel_get_pipe_timings()
7798 tmp = I915_READ(PIPESRC(crtc->pipe)); in intel_get_pipe_timings()
7893 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, in i9xx_crtc_compute_clock() argument
7896 struct drm_device *dev = crtc->base.dev; in i9xx_crtc_compute_clock()
7913 if (connector_state->crtc != &crtc->base) in i9xx_crtc_compute_clock()
7959 i8xx_compute_dpll(crtc, crtc_state, NULL, in i9xx_crtc_compute_clock()
7962 chv_compute_dpll(crtc, crtc_state); in i9xx_crtc_compute_clock()
7964 vlv_compute_dpll(crtc, crtc_state); in i9xx_crtc_compute_clock()
7966 i9xx_compute_dpll(crtc, crtc_state, NULL, in i9xx_crtc_compute_clock()
7973 static void i9xx_get_pfit_config(struct intel_crtc *crtc, in i9xx_get_pfit_config() argument
7976 struct drm_device *dev = crtc->base.dev; in i9xx_get_pfit_config()
7989 if (crtc->pipe != PIPE_B) in i9xx_get_pfit_config()
7992 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) in i9xx_get_pfit_config()
8003 static void vlv_crtc_clock_get(struct intel_crtc *crtc, in vlv_crtc_clock_get() argument
8006 struct drm_device *dev = crtc->base.dev; in vlv_crtc_clock_get()
8031 i9xx_get_initial_plane_config(struct intel_crtc *crtc, in i9xx_get_initial_plane_config() argument
8034 struct drm_device *dev = crtc->base.dev; in i9xx_get_initial_plane_config()
8037 int pipe = crtc->pipe, plane = crtc->plane; in i9xx_get_initial_plane_config()
8099 static void chv_crtc_clock_get(struct intel_crtc *crtc, in chv_crtc_clock_get() argument
8102 struct drm_device *dev = crtc->base.dev; in chv_crtc_clock_get()
8129 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, in i9xx_get_pipe_config() argument
8132 struct drm_device *dev = crtc->base.dev; in i9xx_get_pipe_config()
8137 POWER_DOMAIN_PIPE(crtc->pipe))) in i9xx_get_pipe_config()
8140 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in i9xx_get_pipe_config()
8143 tmp = I915_READ(PIPECONF(crtc->pipe)); in i9xx_get_pipe_config()
8169 intel_get_pipe_timings(crtc, pipe_config); in i9xx_get_pipe_config()
8171 i9xx_get_pfit_config(crtc, pipe_config); in i9xx_get_pipe_config()
8174 tmp = I915_READ(DPLL_MD(crtc->pipe)); in i9xx_get_pipe_config()
8180 tmp = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
8190 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
8200 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); in i9xx_get_pipe_config()
8201 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); in i9xx_get_pipe_config()
8210 chv_crtc_clock_get(crtc, pipe_config); in i9xx_get_pipe_config()
8212 vlv_crtc_clock_get(crtc, pipe_config); in i9xx_get_pipe_config()
8214 i9xx_crtc_clock_get(crtc, pipe_config); in i9xx_get_pipe_config()
8577 struct drm_device *dev = crtc_state->base.crtc->dev; in ironlake_get_refclk()
8587 if (connector_state->crtc != crtc_state->base.crtc) in ironlake_get_refclk()
8611 static void ironlake_set_pipeconf(struct drm_crtc *crtc) in ironlake_set_pipeconf() argument
8613 struct drm_i915_private *dev_priv = crtc->dev->dev_private; in ironlake_set_pipeconf()
8614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_set_pipeconf()
8660 static void intel_set_pipe_csc(struct drm_crtc *crtc) in intel_set_pipe_csc() argument
8662 struct drm_device *dev = crtc->dev; in intel_set_pipe_csc()
8664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_set_pipe_csc()
8717 static void haswell_set_pipeconf(struct drm_crtc *crtc) in haswell_set_pipeconf() argument
8719 struct drm_device *dev = crtc->dev; in haswell_set_pipeconf()
8721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in haswell_set_pipeconf()
8770 static bool ironlake_compute_clocks(struct drm_crtc *crtc, in ironlake_compute_clocks() argument
8776 struct drm_device *dev = crtc->dev; in ironlake_compute_clocks()
8820 struct drm_crtc *crtc = &intel_crtc->base; in ironlake_compute_dpll() local
8821 struct drm_device *dev = crtc->dev; in ironlake_compute_dpll()
8832 if (connector_state->crtc != crtc_state->base.crtc) in ironlake_compute_dpll()
8911 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, in ironlake_crtc_compute_clock() argument
8914 struct drm_device *dev = crtc->base.dev; in ironlake_crtc_compute_clock()
8924 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); in ironlake_crtc_compute_clock()
8929 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, in ironlake_crtc_compute_clock()
8950 dpll = ironlake_compute_dpll(crtc, crtc_state, in ironlake_crtc_compute_clock()
8961 pll = intel_get_shared_dpll(crtc, crtc_state); in ironlake_crtc_compute_clock()
8964 pipe_name(crtc->pipe)); in ironlake_crtc_compute_clock()
8970 crtc->lowfreq_avail = true; in ironlake_crtc_compute_clock()
8972 crtc->lowfreq_avail = false; in ironlake_crtc_compute_clock()
8977 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, in intel_pch_transcoder_get_m_n() argument
8980 struct drm_device *dev = crtc->base.dev; in intel_pch_transcoder_get_m_n()
8982 enum pipe pipe = crtc->pipe; in intel_pch_transcoder_get_m_n()
8993 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, in intel_cpu_transcoder_get_m_n() argument
8998 struct drm_device *dev = crtc->base.dev; in intel_cpu_transcoder_get_m_n()
9000 enum pipe pipe = crtc->pipe; in intel_cpu_transcoder_get_m_n()
9015 crtc->config->has_drrs) { in intel_cpu_transcoder_get_m_n()
9035 void intel_dp_get_m_n(struct intel_crtc *crtc, in intel_dp_get_m_n() argument
9039 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); in intel_dp_get_m_n()
9041 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, in intel_dp_get_m_n()
9046 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, in ironlake_get_fdi_m_n_config() argument
9049 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, in ironlake_get_fdi_m_n_config()
9053 static void skylake_get_pfit_config(struct intel_crtc *crtc, in skylake_get_pfit_config() argument
9056 struct drm_device *dev = crtc->base.dev; in skylake_get_pfit_config()
9064 for (i = 0; i < crtc->num_scalers; i++) { in skylake_get_pfit_config()
9065 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); in skylake_get_pfit_config()
9069 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); in skylake_get_pfit_config()
9070 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); in skylake_get_pfit_config()
9084 skylake_get_initial_plane_config(struct intel_crtc *crtc, in skylake_get_initial_plane_config() argument
9087 struct drm_device *dev = crtc->base.dev; in skylake_get_initial_plane_config()
9090 int pipe = crtc->pipe; in skylake_get_initial_plane_config()
9167 static void ironlake_get_pfit_config(struct intel_crtc *crtc, in ironlake_get_pfit_config() argument
9170 struct drm_device *dev = crtc->base.dev; in ironlake_get_pfit_config()
9174 tmp = I915_READ(PF_CTL(crtc->pipe)); in ironlake_get_pfit_config()
9178 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); in ironlake_get_pfit_config()
9179 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); in ironlake_get_pfit_config()
9186 PF_PIPE_SEL_IVB(crtc->pipe)); in ironlake_get_pfit_config()
9192 ironlake_get_initial_plane_config(struct intel_crtc *crtc, in ironlake_get_initial_plane_config() argument
9195 struct drm_device *dev = crtc->base.dev; in ironlake_get_initial_plane_config()
9198 int pipe = crtc->pipe; in ironlake_get_initial_plane_config()
9260 static bool ironlake_get_pipe_config(struct intel_crtc *crtc, in ironlake_get_pipe_config() argument
9263 struct drm_device *dev = crtc->base.dev; in ironlake_get_pipe_config()
9268 POWER_DOMAIN_PIPE(crtc->pipe))) in ironlake_get_pipe_config()
9271 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in ironlake_get_pipe_config()
9274 tmp = I915_READ(PIPECONF(crtc->pipe)); in ironlake_get_pipe_config()
9298 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { in ironlake_get_pipe_config()
9303 tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); in ironlake_get_pipe_config()
9307 ironlake_get_fdi_m_n_config(crtc, pipe_config); in ironlake_get_pipe_config()
9311 (enum intel_dpll_id) crtc->pipe; in ironlake_get_pipe_config()
9314 if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) in ironlake_get_pipe_config()
9330 ironlake_pch_clock_get(crtc, pipe_config); in ironlake_get_pipe_config()
9335 intel_get_pipe_timings(crtc, pipe_config); in ironlake_get_pipe_config()
9337 ironlake_get_pfit_config(crtc, pipe_config); in ironlake_get_pipe_config()
9345 struct intel_crtc *crtc; in assert_can_disable_lcpll() local
9347 for_each_intel_crtc(dev, crtc) in assert_can_disable_lcpll()
9348 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", in assert_can_disable_lcpll()
9349 pipe_name(crtc->pipe)); in assert_can_disable_lcpll()
9721 static int haswell_crtc_compute_clock(struct intel_crtc *crtc, in haswell_crtc_compute_clock() argument
9724 if (!intel_ddi_pll_select(crtc, crtc_state)) in haswell_crtc_compute_clock()
9727 crtc->lowfreq_avail = false; in haswell_crtc_compute_clock()
9803 static void haswell_get_ddi_port_state(struct intel_crtc *crtc, in haswell_get_ddi_port_state() argument
9806 struct drm_device *dev = crtc->base.dev; in haswell_get_ddi_port_state()
9843 ironlake_get_fdi_m_n_config(crtc, pipe_config); in haswell_get_ddi_port_state()
9847 static bool haswell_get_pipe_config(struct intel_crtc *crtc, in haswell_get_pipe_config() argument
9850 struct drm_device *dev = crtc->base.dev; in haswell_get_pipe_config()
9856 POWER_DOMAIN_PIPE(crtc->pipe))) in haswell_get_pipe_config()
9859 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in haswell_get_pipe_config()
9880 if (trans_edp_pipe == crtc->pipe) in haswell_get_pipe_config()
9892 haswell_get_ddi_port_state(crtc, pipe_config); in haswell_get_pipe_config()
9894 intel_get_pipe_timings(crtc, pipe_config); in haswell_get_pipe_config()
9897 skl_init_scalers(dev, crtc, pipe_config); in haswell_get_pipe_config()
9900 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); in haswell_get_pipe_config()
9909 skylake_get_pfit_config(crtc, pipe_config); in haswell_get_pipe_config()
9911 ironlake_get_pfit_config(crtc, pipe_config); in haswell_get_pipe_config()
9915 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && in haswell_get_pipe_config()
9928 static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on) in i845_update_cursor() argument
9930 struct drm_device *dev = crtc->dev; in i845_update_cursor()
9932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i845_update_cursor()
9990 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on) in i9xx_update_cursor() argument
9992 struct drm_device *dev = crtc->dev; in i9xx_update_cursor()
9994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_update_cursor()
10020 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) in i9xx_update_cursor()
10037 static void intel_crtc_update_cursor(struct drm_crtc *crtc, in intel_crtc_update_cursor() argument
10040 struct drm_device *dev = crtc->dev; in intel_crtc_update_cursor()
10042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_update_cursor()
10044 struct drm_plane_state *cursor_state = crtc->cursor->state; in intel_crtc_update_cursor()
10079 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { in intel_crtc_update_cursor()
10085 i845_update_cursor(crtc, base, on); in intel_crtc_update_cursor()
10087 i9xx_update_cursor(crtc, base, on); in intel_crtc_update_cursor()
10127 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, in intel_crtc_gamma_set() argument
10131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_gamma_set()
10139 intel_crtc_load_lut(crtc); in intel_crtc_gamma_set()
10260 struct drm_crtc *crtc, in intel_modeset_setup_plane_state() argument
10269 plane_state = drm_atomic_get_plane_state(state, crtc->primary); in intel_modeset_setup_plane_state()
10278 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); in intel_modeset_setup_plane_state()
10304 struct drm_crtc *crtc = NULL; in intel_get_load_detect_pipe() local
10333 if (encoder->crtc) { in intel_get_load_detect_pipe()
10334 crtc = encoder->crtc; in intel_get_load_detect_pipe()
10336 ret = drm_modeset_lock(&crtc->mutex, ctx); in intel_get_load_detect_pipe()
10339 ret = drm_modeset_lock(&crtc->primary->mutex, ctx); in intel_get_load_detect_pipe()
10361 crtc = possible_crtc; in intel_get_load_detect_pipe()
10368 if (!crtc) { in intel_get_load_detect_pipe()
10373 ret = drm_modeset_lock(&crtc->mutex, ctx); in intel_get_load_detect_pipe()
10376 ret = drm_modeset_lock(&crtc->primary->mutex, ctx); in intel_get_load_detect_pipe()
10380 intel_crtc = to_intel_crtc(crtc); in intel_get_load_detect_pipe()
10397 connector_state->crtc = crtc; in intel_get_load_detect_pipe()
10430 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); in intel_get_load_detect_pipe()
10442 crtc->primary->crtc = crtc; in intel_get_load_detect_pipe()
10468 struct drm_crtc *crtc = encoder->crtc; in intel_release_load_detect_pipe() local
10469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_release_load_detect_pipe()
10495 connector_state->crtc = NULL; in intel_release_load_detect_pipe()
10499 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, in intel_release_load_detect_pipe()
10543 static void i9xx_crtc_clock_get(struct intel_crtc *crtc, in i9xx_crtc_clock_get() argument
10546 struct drm_device *dev = crtc->base.dev; in i9xx_crtc_clock_get()
10651 static void ironlake_pch_clock_get(struct intel_crtc *crtc, in ironlake_pch_clock_get() argument
10654 struct drm_device *dev = crtc->base.dev; in ironlake_pch_clock_get()
10657 i9xx_crtc_clock_get(crtc, pipe_config); in ironlake_pch_clock_get()
10672 struct drm_crtc *crtc) in intel_crtc_mode_get() argument
10675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_mode_get()
10747 static void intel_crtc_destroy(struct drm_crtc *crtc) in intel_crtc_destroy() argument
10749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_destroy()
10750 struct drm_device *dev = crtc->dev; in intel_crtc_destroy()
10763 drm_crtc_cleanup(crtc); in intel_crtc_destroy()
10772 struct intel_crtc *crtc = to_intel_crtc(work->crtc); in intel_unpin_work_fn() local
10773 struct drm_device *dev = crtc->base.dev; in intel_unpin_work_fn()
10774 struct drm_plane *primary = crtc->base.primary; in intel_unpin_work_fn()
10787 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); in intel_unpin_work_fn()
10788 atomic_dec(&crtc->unpin_work_count); in intel_unpin_work_fn()
10794 struct drm_crtc *crtc) in do_intel_finish_page_flip() argument
10796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in do_intel_finish_page_flip()
10827 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_finish_page_flip() local
10829 do_intel_finish_page_flip(dev, crtc); in intel_finish_page_flip()
10835 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; in intel_finish_page_flip_plane() local
10837 do_intel_finish_page_flip(dev, crtc); in intel_finish_page_flip_plane()
10846 static bool page_flip_finished(struct intel_crtc *crtc) in page_flip_finished() argument
10848 struct drm_device *dev = crtc->base.dev; in page_flip_finished()
10852 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) in page_flip_finished()
10880 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == in page_flip_finished()
10881 crtc->unpin_work->gtt_offset && in page_flip_finished()
10882 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), in page_flip_finished()
10883 crtc->unpin_work->flip_count); in page_flip_finished()
10918 struct drm_crtc *crtc, in intel_gen2_queue_flip() argument
10925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen2_queue_flip()
10953 struct drm_crtc *crtc, in intel_gen3_queue_flip() argument
10960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen3_queue_flip()
10985 struct drm_crtc *crtc, in intel_gen4_queue_flip() argument
10993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen4_queue_flip()
11024 struct drm_crtc *crtc, in intel_gen6_queue_flip() argument
11032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen6_queue_flip()
11060 struct drm_crtc *crtc, in intel_gen7_queue_flip() argument
11067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen7_queue_flip()
11258 struct intel_crtc *crtc = mmio_flip->crtc; in intel_do_mmio_flip() local
11261 spin_lock_irq(&crtc->base.dev->event_lock); in intel_do_mmio_flip()
11262 work = crtc->unpin_work; in intel_do_mmio_flip()
11263 spin_unlock_irq(&crtc->base.dev->event_lock); in intel_do_mmio_flip()
11269 intel_pipe_update_start(crtc); in intel_do_mmio_flip()
11272 skl_do_mmio_flip(crtc, work); in intel_do_mmio_flip()
11275 ilk_do_mmio_flip(crtc, work); in intel_do_mmio_flip()
11277 intel_pipe_update_end(crtc); in intel_do_mmio_flip()
11287 mmio_flip->crtc->reset_counter, in intel_mmio_flip_work_func()
11298 struct drm_crtc *crtc, in intel_queue_mmio_flip() argument
11312 mmio_flip->crtc = to_intel_crtc(crtc); in intel_queue_mmio_flip()
11321 struct drm_crtc *crtc, in intel_default_queue_flip() argument
11331 struct drm_crtc *crtc) in __intel_pageflip_stall_check() argument
11334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in __intel_pageflip_stall_check()
11352 work->flip_ready_vblank = drm_crtc_vblank_count(crtc); in __intel_pageflip_stall_check()
11355 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) in __intel_pageflip_stall_check()
11375 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_check_page_flip() local
11376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_check_page_flip()
11381 if (crtc == NULL) in intel_check_page_flip()
11386 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { in intel_check_page_flip()
11398 static int intel_crtc_page_flip(struct drm_crtc *crtc, in intel_crtc_page_flip() argument
11403 struct drm_device *dev = crtc->dev; in intel_crtc_page_flip()
11405 struct drm_framebuffer *old_fb = crtc->primary->fb; in intel_crtc_page_flip()
11407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_page_flip()
11408 struct drm_plane *primary = crtc->primary; in intel_crtc_page_flip()
11425 if (fb->pixel_format != crtc->primary->fb->pixel_format) in intel_crtc_page_flip()
11433 (fb->offsets[0] != crtc->primary->fb->offsets[0] || in intel_crtc_page_flip()
11434 fb->pitches[0] != crtc->primary->fb->pitches[0])) in intel_crtc_page_flip()
11445 work->crtc = crtc; in intel_crtc_page_flip()
11449 ret = drm_crtc_vblank_get(crtc); in intel_crtc_page_flip()
11459 if (__intel_pageflip_stall_check(dev, crtc)) { in intel_crtc_page_flip()
11466 drm_crtc_vblank_put(crtc); in intel_crtc_page_flip()
11481 crtc->primary->fb = fb; in intel_crtc_page_flip()
11482 update_state_fb(crtc->primary); in intel_crtc_page_flip()
11518 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, in intel_crtc_page_flip()
11519 crtc->primary->state, in intel_crtc_page_flip()
11529 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, in intel_crtc_page_flip()
11543 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, in intel_crtc_page_flip()
11554 work->flip_queued_vblank = drm_crtc_vblank_count(crtc); in intel_crtc_page_flip()
11570 intel_unpin_fb_obj(fb, crtc->primary->state); in intel_crtc_page_flip()
11577 crtc->primary->fb = old_fb; in intel_crtc_page_flip()
11578 update_state_fb(crtc->primary); in intel_crtc_page_flip()
11587 drm_crtc_vblank_put(crtc); in intel_crtc_page_flip()
11599 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); in intel_crtc_page_flip()
11607 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); in intel_crtc_page_flip()
11659 struct drm_crtc *crtc = crtc_state->crtc; in intel_plane_atomic_calc_changes() local
11660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_plane_atomic_calc_changes()
11662 struct drm_device *dev = crtc->dev; in intel_plane_atomic_calc_changes()
11669 bool was_crtc_enabled = crtc->state->active; in intel_plane_atomic_calc_changes()
11772 dev_priv->fbc.crtc == intel_crtc && in intel_plane_atomic_calc_changes()
11807 struct intel_crtc *crtc, in check_single_encoder_cloning() argument
11816 if (connector_state->crtc != &crtc->base) in check_single_encoder_cloning()
11829 struct intel_crtc *crtc) in check_encoder_cloning() argument
11837 if (connector_state->crtc != &crtc->base) in check_encoder_cloning()
11841 if (!check_single_encoder_cloning(state, crtc, encoder)) in check_encoder_cloning()
11848 static int intel_crtc_atomic_check(struct drm_crtc *crtc, in intel_crtc_atomic_check() argument
11851 struct drm_device *dev = crtc->dev; in intel_crtc_atomic_check()
11853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_atomic_check()
11906 connector->base.state->crtc = in intel_modeset_update_connector_atomic_state()
11907 connector->base.encoder->crtc; in intel_modeset_update_connector_atomic_state()
11910 connector->base.state->crtc = NULL; in intel_modeset_update_connector_atomic_state()
11952 compute_baseline_pipe_bpp(struct intel_crtc *crtc, in compute_baseline_pipe_bpp() argument
11955 struct drm_device *dev = crtc->base.dev; in compute_baseline_pipe_bpp()
11975 if (connector_state->crtc != &crtc->base) in compute_baseline_pipe_bpp()
11996 static void intel_dump_pipe_config(struct intel_crtc *crtc, in intel_dump_pipe_config() argument
12000 struct drm_device *dev = crtc->base.dev; in intel_dump_pipe_config()
12006 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, in intel_dump_pipe_config()
12007 context, pipe_config, pipe_name(crtc->pipe)); in intel_dump_pipe_config()
12047 crtc->num_scalers, in intel_dump_pipe_config()
12101 if (intel_plane->pipe != crtc->pipe) in intel_dump_pipe_config()
12111 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, in intel_dump_pipe_config()
12119 crtc->base.primary == plane ? 0 : intel_plane->plane + 1, in intel_dump_pipe_config()
12157 WARN_ON(!connector_state->crtc); in check_digital_port_conflicts()
12215 intel_modeset_pipe_config(struct drm_crtc *crtc, in intel_modeset_pipe_config() argument
12229 (enum transcoder) to_intel_crtc(crtc)->pipe; in intel_modeset_pipe_config()
12244 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), in intel_modeset_pipe_config()
12275 if (connector_state->crtc != crtc) in intel_modeset_pipe_config()
12292 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); in intel_modeset_pipe_config()
12322 struct drm_crtc *crtc; in intel_modeset_update_crtc_state() local
12327 for_each_crtc_in_state(state, crtc, crtc_state, i) { in intel_modeset_update_crtc_state()
12328 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); in intel_modeset_update_crtc_state()
12331 if (crtc->state->active) in intel_modeset_update_crtc_state()
12332 crtc->hwmode = crtc->state->adjusted_mode; in intel_modeset_update_crtc_state()
12334 crtc->hwmode.crtc_clock = 0; in intel_modeset_update_crtc_state()
12726 I915_STATE_WARN(connector->base.state->crtc != in check_encoder_state()
12727 encoder->base.crtc, in check_encoder_state()
12731 I915_STATE_WARN(!!encoder->base.crtc != enabled, in check_encoder_state()
12734 !!encoder->base.crtc, enabled); in check_encoder_state()
12736 if (!encoder->base.crtc) { in check_encoder_state()
12753 struct drm_crtc *crtc; in check_crtc_state() local
12756 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { in check_crtc_state()
12757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in check_crtc_state()
12761 if (!needs_modeset(crtc->state) && in check_crtc_state()
12762 !to_intel_crtc_state(crtc->state)->update_pipe) in check_crtc_state()
12765 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); in check_crtc_state()
12768 pipe_config->base.crtc = crtc; in check_crtc_state()
12772 crtc->base.id); in check_crtc_state()
12780 active = crtc->state->active; in check_crtc_state()
12782 I915_STATE_WARN(crtc->state->active != active, in check_crtc_state()
12784 "(expected %i, found %i)\n", crtc->state->active, active); in check_crtc_state()
12786 I915_STATE_WARN(intel_crtc->active != crtc->state->active, in check_crtc_state()
12788 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); in check_crtc_state()
12790 for_each_encoder_on_crtc(dev, crtc, encoder) { in check_crtc_state()
12794 I915_STATE_WARN(active != crtc->state->active, in check_crtc_state()
12796 encoder->base.base.id, active, crtc->state->active); in check_crtc_state()
12806 if (!crtc->state->active) in check_crtc_state()
12809 sw_config = to_intel_crtc_state(crtc->state); in check_crtc_state()
12825 struct intel_crtc *crtc; in check_shared_dpll_state() local
12851 for_each_intel_crtc(dev, crtc) { in check_shared_dpll_state()
12852 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) in check_shared_dpll_state()
12854 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) in check_shared_dpll_state()
12893 static void update_scanline_offset(struct intel_crtc *crtc) in update_scanline_offset() argument
12895 struct drm_device *dev = crtc->base.dev; in update_scanline_offset()
12916 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; in update_scanline_offset()
12923 crtc->scanline_offset = vtotal - 1; in update_scanline_offset()
12925 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { in update_scanline_offset()
12926 crtc->scanline_offset = 2; in update_scanline_offset()
12928 crtc->scanline_offset = 1; in update_scanline_offset()
12938 struct drm_crtc *crtc; in intel_modeset_clear_plls() local
12945 for_each_crtc_in_state(state, crtc, crtc_state, i) { in intel_modeset_clear_plls()
12948 intel_crtc = to_intel_crtc(crtc); in intel_modeset_clear_plls()
12974 struct drm_crtc *crtc; in haswell_mode_set_planes_workaround() local
12981 for_each_crtc_in_state(state, crtc, crtc_state, i) { in haswell_mode_set_planes_workaround()
12982 intel_crtc = to_intel_crtc(crtc); in haswell_mode_set_planes_workaround()
13031 struct drm_crtc *crtc; in intel_modeset_all_pipes() local
13036 for_each_crtc(state->dev, crtc) { in intel_modeset_all_pipes()
13037 crtc_state = drm_atomic_get_crtc_state(state, crtc); in intel_modeset_all_pipes()
13046 ret = drm_atomic_add_affected_connectors(state, crtc); in intel_modeset_all_pipes()
13050 ret = drm_atomic_add_affected_planes(state, crtc); in intel_modeset_all_pipes()
13106 struct drm_crtc *crtc; in intel_atomic_check() local
13115 for_each_crtc_in_state(state, crtc, crtc_state, i) { in intel_atomic_check()
13119 memset(&to_intel_crtc(crtc)->atomic, 0, in intel_atomic_check()
13123 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) in intel_atomic_check()
13138 ret = drm_atomic_add_affected_connectors(state, crtc); in intel_atomic_check()
13142 ret = intel_modeset_pipe_config(crtc, pipe_config); in intel_atomic_check()
13148 to_intel_crtc_state(crtc->state), in intel_atomic_check()
13157 ret = drm_atomic_add_affected_planes(state, crtc); in intel_atomic_check()
13162 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, in intel_atomic_check()
13200 struct drm_crtc *crtc; in intel_atomic_commit() local
13217 for_each_crtc_in_state(state, crtc, crtc_state, i) { in intel_atomic_commit()
13218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_atomic_commit()
13220 if (!needs_modeset(crtc->state)) in intel_atomic_commit()
13227 intel_crtc_disable_planes(crtc, crtc_state->plane_mask); in intel_atomic_commit()
13228 dev_priv->display.crtc_disable(crtc); in intel_atomic_commit()
13246 for_each_crtc_in_state(state, crtc, crtc_state, i) { in intel_atomic_commit()
13247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_atomic_commit()
13248 bool modeset = needs_modeset(crtc->state); in intel_atomic_commit()
13250 to_intel_crtc_state(crtc->state)->update_pipe; in intel_atomic_commit()
13253 if (modeset && crtc->state->active) { in intel_atomic_commit()
13254 update_scanline_offset(to_intel_crtc(crtc)); in intel_atomic_commit()
13255 dev_priv->display.crtc_enable(crtc); in intel_atomic_commit()
13259 put_domains = modeset_get_crtc_power_domains(crtc); in intel_atomic_commit()
13289 void intel_crtc_restore_mode(struct drm_crtc *crtc) in intel_crtc_restore_mode() argument
13291 struct drm_device *dev = crtc->dev; in intel_crtc_restore_mode()
13299 crtc->base.id); in intel_crtc_restore_mode()
13303 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); in intel_crtc_restore_mode()
13306 crtc_state = drm_atomic_get_crtc_state(state, crtc); in intel_crtc_restore_mode()
13388 struct intel_crtc *crtc; in ibx_pch_dpll_disable() local
13391 for_each_intel_crtc(dev, crtc) { in ibx_pch_dpll_disable()
13392 if (intel_crtc_to_shared_dpll(crtc) == pll) in ibx_pch_dpll_disable()
13393 assert_pch_transcoder_disabled(dev_priv, crtc->pipe); in ibx_pch_dpll_disable()
13544 struct drm_crtc *crtc = state->base.crtc; in intel_check_primary_plane() local
13554 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); in intel_check_primary_plane()
13559 return drm_plane_helper_check_update(plane, crtc, fb, &state->src, in intel_check_primary_plane()
13570 struct drm_crtc *crtc = state->base.crtc; in intel_commit_primary_plane() local
13577 crtc = crtc ? crtc : plane->crtc; in intel_commit_primary_plane()
13578 intel_crtc = to_intel_crtc(crtc); in intel_commit_primary_plane()
13581 crtc->x = src->x1 >> 16; in intel_commit_primary_plane()
13582 crtc->y = src->y1 >> 16; in intel_commit_primary_plane()
13584 if (!crtc->state->active) in intel_commit_primary_plane()
13587 dev_priv->display.update_primary_plane(crtc, fb, in intel_commit_primary_plane()
13594 struct drm_crtc *crtc) in intel_disable_primary_plane() argument
13599 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); in intel_disable_primary_plane()
13602 static void intel_begin_crtc_commit(struct drm_crtc *crtc, in intel_begin_crtc_commit() argument
13605 struct drm_device *dev = crtc->dev; in intel_begin_crtc_commit()
13606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_begin_crtc_commit()
13609 bool modeset = needs_modeset(crtc->state); in intel_begin_crtc_commit()
13612 intel_update_watermarks(crtc); in intel_begin_crtc_commit()
13615 if (crtc->state->active) in intel_begin_crtc_commit()
13621 if (to_intel_crtc_state(crtc->state)->update_pipe) in intel_begin_crtc_commit()
13627 static void intel_finish_crtc_commit(struct drm_crtc *crtc, in intel_finish_crtc_commit() argument
13630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_finish_crtc_commit()
13632 if (crtc->state->active) in intel_finish_crtc_commit()
13743 struct drm_crtc *crtc = crtc_state->base.crtc; in intel_check_cursor_plane() local
13750 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, in intel_check_cursor_plane()
13801 struct drm_crtc *crtc) in intel_disable_cursor_plane() argument
13803 intel_crtc_update_cursor(crtc, false); in intel_disable_cursor_plane()
13810 struct drm_crtc *crtc = state->base.crtc; in intel_commit_cursor_plane() local
13816 crtc = crtc ? crtc : plane->crtc; in intel_commit_cursor_plane()
13817 intel_crtc = to_intel_crtc(crtc); in intel_commit_cursor_plane()
13828 if (crtc->state->active) in intel_commit_cursor_plane()
13829 intel_crtc_update_cursor(crtc, state->visible); in intel_commit_cursor_plane()
13918 crtc_state->base.crtc = &intel_crtc->base; in intel_crtc_init()
13993 if (!encoder || WARN_ON(!encoder->crtc)) in intel_get_pipe_from_connector()
13996 return to_intel_crtc(encoder->crtc)->pipe; in intel_get_pipe_from_connector()
14004 struct intel_crtc *crtc; in intel_get_pipe_from_crtc_id() local
14013 crtc = to_intel_crtc(drmmode_crtc); in intel_get_pipe_from_crtc_id()
14014 pipe_from_crtc_id->pipe = crtc->pipe; in intel_get_pipe_from_crtc_id()
14879 struct intel_crtc *crtc; in intel_modeset_init() local
14975 for_each_intel_crtc(dev, crtc) { in intel_modeset_init()
14978 if (!crtc->active) in intel_modeset_init()
14988 dev_priv->display.get_initial_plane_config(crtc, in intel_modeset_init()
14995 intel_find_initial_plane_obj(crtc, &plane_config); in intel_modeset_init()
15024 intel_check_plane_mapping(struct intel_crtc *crtc) in intel_check_plane_mapping() argument
15026 struct drm_device *dev = crtc->base.dev; in intel_check_plane_mapping()
15033 val = I915_READ(DSPCNTR(!crtc->plane)); in intel_check_plane_mapping()
15036 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) in intel_check_plane_mapping()
15042 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) in intel_crtc_has_encoders() argument
15044 struct drm_device *dev = crtc->base.dev; in intel_crtc_has_encoders()
15047 for_each_encoder_on_crtc(dev, &crtc->base, encoder) in intel_crtc_has_encoders()
15053 static void intel_sanitize_crtc(struct intel_crtc *crtc) in intel_sanitize_crtc() argument
15055 struct drm_device *dev = crtc->base.dev; in intel_sanitize_crtc()
15060 reg = PIPECONF(crtc->config->cpu_transcoder); in intel_sanitize_crtc()
15064 drm_crtc_vblank_reset(&crtc->base); in intel_sanitize_crtc()
15065 if (crtc->active) { in intel_sanitize_crtc()
15068 drm_crtc_vblank_on(&crtc->base); in intel_sanitize_crtc()
15071 for_each_intel_plane_on_crtc(dev, crtc, plane) { in intel_sanitize_crtc()
15075 plane->disable_plane(&plane->base, &crtc->base); in intel_sanitize_crtc()
15082 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { in intel_sanitize_crtc()
15086 crtc->base.base.id); in intel_sanitize_crtc()
15091 plane = crtc->plane; in intel_sanitize_crtc()
15092 to_intel_plane_state(crtc->base.primary->state)->visible = true; in intel_sanitize_crtc()
15093 crtc->plane = !plane; in intel_sanitize_crtc()
15094 intel_crtc_disable_noatomic(&crtc->base); in intel_sanitize_crtc()
15095 crtc->plane = plane; in intel_sanitize_crtc()
15099 crtc->pipe == PIPE_A && !crtc->active) { in intel_sanitize_crtc()
15109 if (!intel_crtc_has_encoders(crtc)) in intel_sanitize_crtc()
15110 intel_crtc_disable_noatomic(&crtc->base); in intel_sanitize_crtc()
15112 if (crtc->active != crtc->base.state->active) { in intel_sanitize_crtc()
15120 crtc->base.base.id, in intel_sanitize_crtc()
15121 crtc->base.state->enable ? "enabled" : "disabled", in intel_sanitize_crtc()
15122 crtc->active ? "enabled" : "disabled"); in intel_sanitize_crtc()
15124 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); in intel_sanitize_crtc()
15125 crtc->base.state->active = crtc->active; in intel_sanitize_crtc()
15126 crtc->base.enabled = crtc->active; in intel_sanitize_crtc()
15133 WARN_ON(crtc->active); in intel_sanitize_crtc()
15135 for_each_encoder_on_crtc(dev, &crtc->base, encoder) in intel_sanitize_crtc()
15136 encoder->base.crtc = NULL; in intel_sanitize_crtc()
15139 if (crtc->active || HAS_GMCH_DISPLAY(dev)) { in intel_sanitize_crtc()
15153 crtc->cpu_fifo_underrun_disabled = true; in intel_sanitize_crtc()
15154 crtc->pch_fifo_underrun_disabled = true; in intel_sanitize_crtc()
15167 bool has_active_crtc = encoder->base.crtc && in intel_sanitize_encoder()
15168 to_intel_crtc(encoder->base.crtc)->active; in intel_sanitize_encoder()
15186 if (encoder->base.crtc) { in intel_sanitize_encoder()
15194 encoder->base.crtc = NULL; in intel_sanitize_encoder()
15247 static void readout_plane_state(struct intel_crtc *crtc) in readout_plane_state() argument
15249 struct drm_plane *primary = crtc->base.primary; in readout_plane_state()
15257 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); in readout_plane_state()
15264 struct intel_crtc *crtc; in intel_modeset_readout_hw_state() local
15269 for_each_intel_crtc(dev, crtc) { in intel_modeset_readout_hw_state()
15270 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state); in intel_modeset_readout_hw_state()
15271 memset(crtc->config, 0, sizeof(*crtc->config)); in intel_modeset_readout_hw_state()
15272 crtc->config->base.crtc = &crtc->base; in intel_modeset_readout_hw_state()
15274 crtc->active = dev_priv->display.get_pipe_config(crtc, in intel_modeset_readout_hw_state()
15275 crtc->config); in intel_modeset_readout_hw_state()
15277 crtc->base.state->active = crtc->active; in intel_modeset_readout_hw_state()
15278 crtc->base.enabled = crtc->active; in intel_modeset_readout_hw_state()
15280 readout_plane_state(crtc); in intel_modeset_readout_hw_state()
15283 crtc->base.base.id, in intel_modeset_readout_hw_state()
15284 crtc->active ? "enabled" : "disabled"); in intel_modeset_readout_hw_state()
15294 for_each_intel_crtc(dev, crtc) { in intel_modeset_readout_hw_state()
15295 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { in intel_modeset_readout_hw_state()
15297 pll->config.crtc_mask |= 1 << crtc->pipe; in intel_modeset_readout_hw_state()
15312 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in intel_modeset_readout_hw_state()
15313 encoder->base.crtc = &crtc->base; in intel_modeset_readout_hw_state()
15314 encoder->get_config(encoder, crtc->config); in intel_modeset_readout_hw_state()
15316 encoder->base.crtc = NULL; in intel_modeset_readout_hw_state()
15322 encoder->base.crtc ? "enabled" : "disabled", in intel_modeset_readout_hw_state()
15340 for_each_intel_crtc(dev, crtc) { in intel_modeset_readout_hw_state()
15341 crtc->base.hwmode = crtc->config->base.adjusted_mode; in intel_modeset_readout_hw_state()
15343 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); in intel_modeset_readout_hw_state()
15344 if (crtc->base.state->active) { in intel_modeset_readout_hw_state()
15345 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); in intel_modeset_readout_hw_state()
15346 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); in intel_modeset_readout_hw_state()
15347 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); in intel_modeset_readout_hw_state()
15366 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; in intel_modeset_readout_hw_state()
15368 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); in intel_modeset_readout_hw_state()
15369 update_scanline_offset(crtc); in intel_modeset_readout_hw_state()
15382 struct intel_crtc *crtc; in intel_modeset_setup_hw_state() local
15394 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in intel_modeset_setup_hw_state()
15395 intel_sanitize_crtc(crtc); in intel_modeset_setup_hw_state()
15396 intel_dump_pipe_config(crtc, crtc->config, in intel_modeset_setup_hw_state()
15421 for_each_intel_crtc(dev, crtc) { in intel_modeset_setup_hw_state()
15424 put_domains = modeset_get_crtc_power_domains(&crtc->base); in intel_modeset_setup_hw_state()
15436 struct drm_crtc *crtc; in intel_display_resume() local
15447 for_each_crtc(dev, crtc) { in intel_display_resume()
15449 drm_atomic_get_crtc_state(state, crtc); in intel_display_resume()
15518 c->primary->crtc = c->primary->state->crtc = NULL; in intel_modeset_gem_init()
15814 struct intel_crtc *crtc; in intel_modeset_preclose() local
15816 for_each_intel_crtc(dev, crtc) { in intel_modeset_preclose()
15821 work = crtc->unpin_work; in intel_modeset_preclose()