1875 	WARN_ON(!pll->config.crtc_mask);  in intel_prepare_shared_dpll()
1902 	if (WARN_ON(pll->config.crtc_mask == 0))  in intel_enable_shared_dpll()
1936 	if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))  in intel_disable_shared_dpll()
4269 		WARN_ON(shared_dpll[i].crtc_mask);  in intel_get_shared_dpll()
4289 		WARN_ON(shared_dpll[i].crtc_mask);  in intel_get_shared_dpll()
4300 		if (shared_dpll[i].crtc_mask == 0)  in intel_get_shared_dpll()
4308 				      shared_dpll[i].crtc_mask,  in intel_get_shared_dpll()
4317 		if (shared_dpll[i].crtc_mask == 0) {  in intel_get_shared_dpll()
4327 	if (shared_dpll[i].crtc_mask == 0)  in intel_get_shared_dpll()
4335 	shared_dpll[i].crtc_mask |= 1 << crtc->pipe;  in intel_get_shared_dpll()
6353 	unsigned crtc_mask = 0;  in intel_display_suspend()  local
6379 		crtc_mask |= 1 << drm_crtc_index(crtc);  in intel_display_suspend()
6382 	if (crtc_mask) {  in intel_display_suspend()
6387 				if (crtc_mask & (1 << drm_crtc_index(crtc)))  in intel_display_suspend()
12840 		I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),  in check_shared_dpll_state()
12842 		     pll->active, hweight32(pll->config.crtc_mask));  in check_shared_dpll_state()
12860 		I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,  in check_shared_dpll_state()
12862 		     hweight32(pll->config.crtc_mask), enabled_crtcs);  in check_shared_dpll_state()
12960 		shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);  in intel_modeset_clear_plls()
14227 		encoder->base.possible_crtcs = encoder->crtc_mask;  in intel_setup_outputs()
15293 		pll->config.crtc_mask = 0;  in intel_modeset_readout_hw_state()
15297 				pll->config.crtc_mask |= 1 << crtc->pipe;  in intel_modeset_readout_hw_state()
15302 			      pll->name, pll->config.crtc_mask, pll->on);  in intel_modeset_readout_hw_state()
15304 		if (pll->config.crtc_mask)  in intel_modeset_readout_hw_state()