Lines Matching refs:crtc_state
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
528 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, in intel_pipe_will_have_type() argument
531 struct drm_atomic_state *state = crtc_state->base.state; in intel_pipe_will_have_type()
538 if (connector_state->crtc != crtc_state->base.crtc) in intel_pipe_will_have_type()
554 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) in intel_ironlake_limit() argument
556 struct drm_device *dev = crtc_state->base.crtc->dev; in intel_ironlake_limit()
559 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { in intel_ironlake_limit()
578 intel_g4x_limit(struct intel_crtc_state *crtc_state) in intel_g4x_limit() argument
580 struct drm_device *dev = crtc_state->base.crtc->dev; in intel_g4x_limit()
583 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { in intel_g4x_limit()
588 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || in intel_g4x_limit()
589 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { in intel_g4x_limit()
591 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { in intel_g4x_limit()
600 intel_limit(struct intel_crtc_state *crtc_state, int refclk) in intel_limit() argument
602 struct drm_device *dev = crtc_state->base.crtc->dev; in intel_limit()
608 limit = intel_ironlake_limit(crtc_state, refclk); in intel_limit()
610 limit = intel_g4x_limit(crtc_state); in intel_limit()
612 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) in intel_limit()
621 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) in intel_limit()
626 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) in intel_limit()
628 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) in intel_limit()
742 const struct intel_crtc_state *crtc_state, in i9xx_select_p2_div() argument
745 struct drm_device *dev = crtc_state->base.crtc->dev; in i9xx_select_p2_div()
747 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { in i9xx_select_p2_div()
767 struct intel_crtc_state *crtc_state, in i9xx_find_best_dpll() argument
771 struct drm_device *dev = crtc_state->base.crtc->dev; in i9xx_find_best_dpll()
777 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); in i9xx_find_best_dpll()
814 struct intel_crtc_state *crtc_state, in pnv_find_best_dpll() argument
818 struct drm_device *dev = crtc_state->base.crtc->dev; in pnv_find_best_dpll()
824 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); in pnv_find_best_dpll()
859 struct intel_crtc_state *crtc_state, in g4x_find_best_dpll() argument
863 struct drm_device *dev = crtc_state->base.crtc->dev; in g4x_find_best_dpll()
872 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); in g4x_find_best_dpll()
947 struct intel_crtc_state *crtc_state, in vlv_find_best_dpll() argument
951 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in vlv_find_best_dpll()
1001 struct intel_crtc_state *crtc_state, in chv_find_best_dpll() argument
1005 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in chv_find_best_dpll()
1057 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, in bxt_find_best_dpll() argument
1060 int refclk = i9xx_get_refclk(crtc_state, 0); in bxt_find_best_dpll()
1062 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, in bxt_find_best_dpll()
2611 struct drm_crtc_state *crtc_state = intel_crtc->base.state; in intel_find_initial_plane_obj() local
2657 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); in intel_find_initial_plane_obj()
3103 struct intel_crtc_state *crtc_state = intel_crtc->config; in skylake_update_primary_plane() local
3177 crtc_state->scaler_state.scalers[scaler_id].mode; in skylake_update_primary_plane()
4251 struct intel_crtc_state *crtc_state) in intel_get_shared_dpll() argument
4259 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); in intel_get_shared_dpll()
4279 encoder = intel_ddi_get_crtc_new_encoder(crtc_state); in intel_get_shared_dpll()
4303 if (memcmp(&crtc_state->dpll_hw_state, in intel_get_shared_dpll()
4305 sizeof(crtc_state->dpll_hw_state)) == 0) { in intel_get_shared_dpll()
4329 crtc_state->dpll_hw_state; in intel_get_shared_dpll()
4331 crtc_state->shared_dpll = i; in intel_get_shared_dpll()
4372 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, in skl_update_scaler() argument
4377 &crtc_state->scaler_state; in skl_update_scaler()
4379 to_intel_crtc(crtc_state->base.crtc); in skl_update_scaler()
4465 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, in skl_update_scaler_plane() argument
4469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); in skl_update_scaler_plane()
4481 ret = skl_update_scaler(crtc_state, force_detach, in skl_update_scaler_plane()
5356 struct drm_crtc_state *crtc_state; in modeset_update_crtc_power_domains() local
5360 for_each_crtc_in_state(state, crtc, crtc_state, i) { in modeset_update_crtc_power_domains()
6024 struct intel_crtc_state *crtc_state; in intel_mode_max_pixclk() local
6028 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); in intel_mode_max_pixclk()
6029 if (IS_ERR(crtc_state)) in intel_mode_max_pixclk()
6030 return PTR_ERR(crtc_state); in intel_mode_max_pixclk()
6032 if (!crtc_state->base.enable) in intel_mode_max_pixclk()
6036 crtc_state->base.adjusted_mode.crtc_clock); in intel_mode_max_pixclk()
6368 struct drm_crtc_state *crtc_state = in intel_display_suspend() local
6371 ret = PTR_ERR_OR_ZERO(crtc_state); in intel_display_suspend()
6375 if (!crtc_state->active) in intel_display_suspend()
6378 crtc_state->active = false; in intel_display_suspend()
6487 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) in pipe_required_fdi_lanes() argument
6489 if (crtc_state->base.enable && crtc_state->has_pch_encoder) in pipe_required_fdi_lanes()
6490 return crtc_state->fdi_lanes; in pipe_required_fdi_lanes()
7138 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, in i9xx_get_refclk() argument
7141 struct drm_device *dev = crtc_state->base.crtc->dev; in i9xx_get_refclk()
7145 WARN_ON(!crtc_state->base.state); in i9xx_get_refclk()
7149 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && in i9xx_get_refclk()
7173 struct intel_crtc_state *crtc_state, in i9xx_update_pll_dividers() argument
7180 fp = pnv_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
7184 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
7189 crtc_state->dpll_hw_state.fp0 = fp; in i9xx_update_pll_dividers()
7192 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && in i9xx_update_pll_dividers()
7194 crtc_state->dpll_hw_state.fp1 = fp2; in i9xx_update_pll_dividers()
7197 crtc_state->dpll_hw_state.fp1 = fp; in i9xx_update_pll_dividers()
7582 struct intel_crtc_state *crtc_state, in i9xx_compute_dpll() argument
7590 struct dpll *clock = &crtc_state->dpll; in i9xx_compute_dpll()
7592 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); in i9xx_compute_dpll()
7594 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || in i9xx_compute_dpll()
7595 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); in i9xx_compute_dpll()
7599 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) in i9xx_compute_dpll()
7605 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
7612 if (crtc_state->has_dp_encoder) in i9xx_compute_dpll()
7640 if (crtc_state->sdvo_tv_clock) in i9xx_compute_dpll()
7642 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && in i9xx_compute_dpll()
7649 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
7652 u32 dpll_md = (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
7654 crtc_state->dpll_hw_state.dpll_md = dpll_md; in i9xx_compute_dpll()
7659 struct intel_crtc_state *crtc_state, in i8xx_compute_dpll() argument
7666 struct dpll *clock = &crtc_state->dpll; in i8xx_compute_dpll()
7668 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); in i8xx_compute_dpll()
7672 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { in i8xx_compute_dpll()
7683 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) in i8xx_compute_dpll()
7686 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && in i8xx_compute_dpll()
7693 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
7894 struct intel_crtc_state *crtc_state) in i9xx_crtc_compute_clock() argument
7904 struct drm_atomic_state *state = crtc_state->base.state; in i9xx_crtc_compute_clock()
7909 memset(&crtc_state->dpll_hw_state, 0, in i9xx_crtc_compute_clock()
7910 sizeof(crtc_state->dpll_hw_state)); in i9xx_crtc_compute_clock()
7932 if (!crtc_state->clock_set) { in i9xx_crtc_compute_clock()
7933 refclk = i9xx_get_refclk(crtc_state, num_connectors); in i9xx_crtc_compute_clock()
7941 limit = intel_limit(crtc_state, refclk); in i9xx_crtc_compute_clock()
7942 ok = dev_priv->display.find_dpll(limit, crtc_state, in i9xx_crtc_compute_clock()
7943 crtc_state->port_clock, in i9xx_crtc_compute_clock()
7951 crtc_state->dpll.n = clock.n; in i9xx_crtc_compute_clock()
7952 crtc_state->dpll.m1 = clock.m1; in i9xx_crtc_compute_clock()
7953 crtc_state->dpll.m2 = clock.m2; in i9xx_crtc_compute_clock()
7954 crtc_state->dpll.p1 = clock.p1; in i9xx_crtc_compute_clock()
7955 crtc_state->dpll.p2 = clock.p2; in i9xx_crtc_compute_clock()
7959 i8xx_compute_dpll(crtc, crtc_state, NULL, in i9xx_crtc_compute_clock()
7962 chv_compute_dpll(crtc, crtc_state); in i9xx_crtc_compute_clock()
7964 vlv_compute_dpll(crtc, crtc_state); in i9xx_crtc_compute_clock()
7966 i9xx_compute_dpll(crtc, crtc_state, NULL, in i9xx_crtc_compute_clock()
8575 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) in ironlake_get_refclk() argument
8577 struct drm_device *dev = crtc_state->base.crtc->dev; in ironlake_get_refclk()
8579 struct drm_atomic_state *state = crtc_state->base.state; in ironlake_get_refclk()
8587 if (connector_state->crtc != crtc_state->base.crtc) in ironlake_get_refclk()
8771 struct intel_crtc_state *crtc_state, in ironlake_compute_clocks() argument
8782 refclk = ironlake_get_refclk(crtc_state); in ironlake_compute_clocks()
8789 limit = intel_limit(crtc_state, refclk); in ironlake_compute_clocks()
8790 ret = dev_priv->display.find_dpll(limit, crtc_state, in ironlake_compute_clocks()
8791 crtc_state->port_clock, in ironlake_compute_clocks()
8816 struct intel_crtc_state *crtc_state, in ironlake_compute_dpll() argument
8823 struct drm_atomic_state *state = crtc_state->base.state; in ironlake_compute_dpll()
8832 if (connector_state->crtc != crtc_state->base.crtc) in ironlake_compute_dpll()
8859 } else if (crtc_state->sdvo_tv_clock) in ironlake_compute_dpll()
8862 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) in ironlake_compute_dpll()
8875 dpll |= (crtc_state->pixel_multiplier - 1) in ironlake_compute_dpll()
8880 if (crtc_state->has_dp_encoder) in ironlake_compute_dpll()
8884 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ironlake_compute_dpll()
8886 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ironlake_compute_dpll()
8888 switch (crtc_state->dpll.p2) { in ironlake_compute_dpll()
8912 struct intel_crtc_state *crtc_state) in ironlake_crtc_compute_clock() argument
8921 memset(&crtc_state->dpll_hw_state, 0, in ironlake_crtc_compute_clock()
8922 sizeof(crtc_state->dpll_hw_state)); in ironlake_crtc_compute_clock()
8929 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, in ironlake_crtc_compute_clock()
8931 if (!ok && !crtc_state->clock_set) { in ironlake_crtc_compute_clock()
8936 if (!crtc_state->clock_set) { in ironlake_crtc_compute_clock()
8937 crtc_state->dpll.n = clock.n; in ironlake_crtc_compute_clock()
8938 crtc_state->dpll.m1 = clock.m1; in ironlake_crtc_compute_clock()
8939 crtc_state->dpll.m2 = clock.m2; in ironlake_crtc_compute_clock()
8940 crtc_state->dpll.p1 = clock.p1; in ironlake_crtc_compute_clock()
8941 crtc_state->dpll.p2 = clock.p2; in ironlake_crtc_compute_clock()
8945 if (crtc_state->has_pch_encoder) { in ironlake_crtc_compute_clock()
8946 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in ironlake_crtc_compute_clock()
8950 dpll = ironlake_compute_dpll(crtc, crtc_state, in ironlake_crtc_compute_clock()
8954 crtc_state->dpll_hw_state.dpll = dpll; in ironlake_crtc_compute_clock()
8955 crtc_state->dpll_hw_state.fp0 = fp; in ironlake_crtc_compute_clock()
8957 crtc_state->dpll_hw_state.fp1 = fp2; in ironlake_crtc_compute_clock()
8959 crtc_state->dpll_hw_state.fp1 = fp; in ironlake_crtc_compute_clock()
8961 pll = intel_get_shared_dpll(crtc, crtc_state); in ironlake_crtc_compute_clock()
9577 struct intel_crtc_state *crtc_state; in ilk_max_pixel_rate() local
9583 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); in ilk_max_pixel_rate()
9584 if (IS_ERR(crtc_state)) in ilk_max_pixel_rate()
9585 return PTR_ERR(crtc_state); in ilk_max_pixel_rate()
9587 if (!crtc_state->base.enable) in ilk_max_pixel_rate()
9590 pixel_rate = ilk_pipe_pixel_rate(crtc_state); in ilk_max_pixel_rate()
9593 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled) in ilk_max_pixel_rate()
9722 struct intel_crtc_state *crtc_state) in haswell_crtc_compute_clock() argument
9724 if (!intel_ddi_pll_select(crtc, crtc_state)) in haswell_crtc_compute_clock()
10310 struct intel_crtc_state *crtc_state; in intel_get_load_detect_pipe() local
10400 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); in intel_get_load_detect_pipe()
10401 if (IS_ERR(crtc_state)) { in intel_get_load_detect_pipe()
10402 ret = PTR_ERR(crtc_state); in intel_get_load_detect_pipe()
10406 crtc_state->base.active = crtc_state->base.enable = true; in intel_get_load_detect_pipe()
10434 drm_mode_copy(&crtc_state->base.mode, mode); in intel_get_load_detect_pipe()
10472 struct intel_crtc_state *crtc_state; in intel_release_load_detect_pipe() local
10490 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); in intel_release_load_detect_pipe()
10491 if (IS_ERR(crtc_state)) in intel_release_load_detect_pipe()
10497 crtc_state->base.enable = crtc_state->base.active = false; in intel_release_load_detect_pipe()
11656 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, in intel_plane_atomic_calc_changes() argument
11659 struct drm_crtc *crtc = crtc_state->crtc; in intel_plane_atomic_calc_changes()
11668 bool mode_changed = needs_modeset(crtc_state); in intel_plane_atomic_calc_changes()
11670 bool is_crtc_enabled = crtc_state->active; in intel_plane_atomic_calc_changes()
11675 if (crtc_state && INTEL_INFO(dev)->gen >= 9 && in intel_plane_atomic_calc_changes()
11678 to_intel_crtc_state(crtc_state), in intel_plane_atomic_calc_changes()
11849 struct drm_crtc_state *crtc_state) in intel_crtc_atomic_check() argument
11855 to_intel_crtc_state(crtc_state); in intel_crtc_atomic_check()
11856 struct drm_atomic_state *state = crtc_state->state; in intel_crtc_atomic_check()
11858 bool mode_changed = needs_modeset(crtc_state); in intel_crtc_atomic_check()
11865 if (mode_changed && !crtc_state->active) in intel_crtc_atomic_check()
11868 if (mode_changed && crtc_state->enable && in intel_crtc_atomic_check()
12183 clear_intel_crtc_state(struct intel_crtc_state *crtc_state) in clear_intel_crtc_state() argument
12197 tmp_state = crtc_state->base; in clear_intel_crtc_state()
12198 scaler_state = crtc_state->scaler_state; in clear_intel_crtc_state()
12199 shared_dpll = crtc_state->shared_dpll; in clear_intel_crtc_state()
12200 dpll_hw_state = crtc_state->dpll_hw_state; in clear_intel_crtc_state()
12201 ddi_pll_sel = crtc_state->ddi_pll_sel; in clear_intel_crtc_state()
12202 force_thru = crtc_state->pch_pfit.force_thru; in clear_intel_crtc_state()
12204 memset(crtc_state, 0, sizeof *crtc_state); in clear_intel_crtc_state()
12206 crtc_state->base = tmp_state; in clear_intel_crtc_state()
12207 crtc_state->scaler_state = scaler_state; in clear_intel_crtc_state()
12208 crtc_state->shared_dpll = shared_dpll; in clear_intel_crtc_state()
12209 crtc_state->dpll_hw_state = dpll_hw_state; in clear_intel_crtc_state()
12210 crtc_state->ddi_pll_sel = ddi_pll_sel; in clear_intel_crtc_state()
12211 crtc_state->pch_pfit.force_thru = force_thru; in clear_intel_crtc_state()
12323 struct drm_crtc_state *crtc_state; in intel_modeset_update_crtc_state() local
12327 for_each_crtc_in_state(state, crtc, crtc_state, i) { in intel_modeset_update_crtc_state()
12939 struct drm_crtc_state *crtc_state; in intel_modeset_clear_plls() local
12945 for_each_crtc_in_state(state, crtc, crtc_state, i) { in intel_modeset_clear_plls()
12949 intel_crtc_state = to_intel_crtc_state(crtc_state); in intel_modeset_clear_plls()
12952 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) in intel_modeset_clear_plls()
12972 struct drm_crtc_state *crtc_state; in haswell_mode_set_planes_workaround() local
12981 for_each_crtc_in_state(state, crtc, crtc_state, i) { in haswell_mode_set_planes_workaround()
12984 if (!crtc_state->active || !needs_modeset(crtc_state)) in haswell_mode_set_planes_workaround()
12988 other_crtc_state = to_intel_crtc_state(crtc_state); in haswell_mode_set_planes_workaround()
12991 first_crtc_state = to_intel_crtc_state(crtc_state); in haswell_mode_set_planes_workaround()
13032 struct drm_crtc_state *crtc_state; in intel_modeset_all_pipes() local
13037 crtc_state = drm_atomic_get_crtc_state(state, crtc); in intel_modeset_all_pipes()
13038 if (IS_ERR(crtc_state)) in intel_modeset_all_pipes()
13039 return PTR_ERR(crtc_state); in intel_modeset_all_pipes()
13041 if (!crtc_state->active || needs_modeset(crtc_state)) in intel_modeset_all_pipes()
13044 crtc_state->mode_changed = true; in intel_modeset_all_pipes()
13107 struct drm_crtc_state *crtc_state; in intel_atomic_check() local
13115 for_each_crtc_in_state(state, crtc, crtc_state, i) { in intel_atomic_check()
13117 to_intel_crtc_state(crtc_state); in intel_atomic_check()
13123 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) in intel_atomic_check()
13124 crtc_state->mode_changed = true; in intel_atomic_check()
13126 if (!crtc_state->enable) { in intel_atomic_check()
13127 if (needs_modeset(crtc_state)) in intel_atomic_check()
13132 if (!needs_modeset(crtc_state)) in intel_atomic_check()
13150 crtc_state->mode_changed = false; in intel_atomic_check()
13151 to_intel_crtc_state(crtc_state)->update_pipe = true; in intel_atomic_check()
13154 if (needs_modeset(crtc_state)) { in intel_atomic_check()
13163 needs_modeset(crtc_state) ? in intel_atomic_check()
13201 struct drm_crtc_state *crtc_state; in intel_atomic_commit() local
13217 for_each_crtc_in_state(state, crtc, crtc_state, i) { in intel_atomic_commit()
13226 if (crtc_state->active) { in intel_atomic_commit()
13227 intel_crtc_disable_planes(crtc, crtc_state->plane_mask); in intel_atomic_commit()
13246 for_each_crtc_in_state(state, crtc, crtc_state, i) { in intel_atomic_commit()
13268 drm_atomic_helper_commit_planes_on_crtc(crtc_state); in intel_atomic_commit()
13293 struct drm_crtc_state *crtc_state; in intel_crtc_restore_mode() local
13306 crtc_state = drm_atomic_get_crtc_state(state, crtc); in intel_crtc_restore_mode()
13307 ret = PTR_ERR_OR_ZERO(crtc_state); in intel_crtc_restore_mode()
13309 if (!crtc_state->active) in intel_crtc_restore_mode()
13312 crtc_state->mode_changed = true; in intel_crtc_restore_mode()
13510 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) in skl_max_scale() argument
13517 if (!intel_crtc || !crtc_state) in skl_max_scale()
13522 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; in skl_max_scale()
13523 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; in skl_max_scale()
13541 struct intel_crtc_state *crtc_state, in intel_check_primary_plane() argument
13554 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); in intel_check_primary_plane()
13740 struct intel_crtc_state *crtc_state, in intel_check_cursor_plane() argument
13743 struct drm_crtc *crtc = crtc_state->base.crtc; in intel_check_cursor_plane()
13885 struct intel_crtc_state *crtc_state) in skl_init_scalers() argument
13889 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; in skl_init_scalers()
13904 struct intel_crtc_state *crtc_state = NULL; in intel_crtc_init() local
13913 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); in intel_crtc_init()
13914 if (!crtc_state) in intel_crtc_init()
13916 intel_crtc->config = crtc_state; in intel_crtc_init()
13917 intel_crtc->base.state = &crtc_state->base; in intel_crtc_init()
13918 crtc_state->base.crtc = &intel_crtc->base; in intel_crtc_init()
13927 skl_init_scalers(dev, intel_crtc, crtc_state); in intel_crtc_init()
13982 kfree(crtc_state); in intel_crtc_init()
15448 struct drm_crtc_state *crtc_state = in intel_display_resume() local
15451 ret = PTR_ERR_OR_ZERO(crtc_state); in intel_display_resume()
15456 crtc_state->mode_changed = true; in intel_display_resume()