132 	intel_range_t   dot, vco, n, m, m1, m2, p, p1;  member
244 	.p1 = { .min = 2, .max = 33 },
257 	.p1 = { .min = 2, .max = 33 },
270 	.p1 = { .min = 1, .max = 6 },
283 	.p1 = { .min = 1, .max = 8 },
296 	.p1 = { .min = 1, .max = 8 },
310 	.p1 = { .min = 1, .max = 3},
325 	.p1 = { .min = 1, .max = 8},
338 	.p1 = { .min = 2, .max = 8 },
352 	.p1 = { .min = 2, .max = 6 },
368 	.p1 = { .min = 1, .max = 8 },
381 	.p1 = { .min = 1, .max = 8 },
399 	.p1 = { .min = 1, .max = 8 },
412 	.p1 = { .min = 2, .max = 8 },
425 	.p1 = { .min = 2, .max = 8 },
439 	.p1 = { .min = 2, .max = 8 },
452 	.p1 = { .min = 2, .max = 6 },
469 	.p1 = { .min = 2, .max = 3 },
485 	.p1 = { .min = 2, .max = 4 },
497 	.p1 = { .min = 2, .max = 4 },
648 	clock->p = clock->p1 * clock->p2;  in pnv_calc_dpll_params()
665 	clock->p = clock->p1 * clock->p2;  in i9xx_calc_dpll_params()
677 	clock->p = clock->p1 * clock->p2;  in vlv_calc_dpll_params()
689 	clock->p = clock->p1 * clock->p2;  in chv_calc_dpll_params()
711 	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)  in intel_PLL_is_valid()
787 				for (clock.p1 = limit->p1.min;  in i9xx_find_best_dpll()
788 					clock.p1 <= limit->p1.max; clock.p1++) {  in i9xx_find_best_dpll()
832 				for (clock.p1 = limit->p1.min;  in pnv_find_best_dpll()
833 					clock.p1 <= limit->p1.max; clock.p1++) {  in pnv_find_best_dpll()
882 				for (clock.p1 = limit->p1.max;  in g4x_find_best_dpll()
883 				     clock.p1 >= limit->p1.min; clock.p1--) {  in g4x_find_best_dpll()
965 		for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {  in vlv_find_best_dpll()
968 				clock.p = clock.p1 * clock.p2;  in vlv_find_best_dpll()
1023 	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {  in chv_find_best_dpll()
1029 			clock.p = clock.p1 * clock.p2;  in chv_find_best_dpll()
7340 	bestp1 = pipe_config->dpll.p1;  in vlv_prepare_pll()
7446 	bestp1 = pipe_config->dpll.p1;  in chv_prepare_pll()
7617 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;  in i9xx_compute_dpll()
7619 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;  in i9xx_compute_dpll()
7621 			dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;  in i9xx_compute_dpll()
7673 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;  in i8xx_compute_dpll()
7675 		if (clock->p1 == 2)  in i8xx_compute_dpll()
7678 			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;  in i8xx_compute_dpll()
7954 		crtc_state->dpll.p1 = clock.p1;  in i9xx_crtc_compute_clock()
8024 	clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;  in vlv_crtc_clock_get()
8123 	clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;  in chv_crtc_clock_get()
8884 	dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;  in ironlake_compute_dpll()
8886 	dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;  in ironlake_compute_dpll()
8940 		crtc_state->dpll.p1 = clock.p1;  in ironlake_crtc_compute_clock()
10571 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>  in i9xx_crtc_clock_get()
10574 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>  in i9xx_crtc_clock_get()
10601 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>  in i9xx_crtc_clock_get()
10610 				clock.p1 = 2;  in i9xx_crtc_clock_get()
10612 				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>  in i9xx_crtc_clock_get()