Lines Matching refs:pll
1202 struct intel_shared_dpll *pll, in assert_shared_dpll() argument
1208 if (WARN (!pll, in assert_shared_dpll()
1212 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); in assert_shared_dpll()
1215 pll->name, state_string(state), state_string(cur_state)); in assert_shared_dpll()
1870 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); in intel_prepare_shared_dpll() local
1872 if (WARN_ON(pll == NULL)) in intel_prepare_shared_dpll()
1875 WARN_ON(!pll->config.crtc_mask); in intel_prepare_shared_dpll()
1876 if (pll->active == 0) { in intel_prepare_shared_dpll()
1877 DRM_DEBUG_DRIVER("setting up %s\n", pll->name); in intel_prepare_shared_dpll()
1878 WARN_ON(pll->on); in intel_prepare_shared_dpll()
1879 assert_shared_dpll_disabled(dev_priv, pll); in intel_prepare_shared_dpll()
1881 pll->mode_set(dev_priv, pll); in intel_prepare_shared_dpll()
1897 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); in intel_enable_shared_dpll() local
1899 if (WARN_ON(pll == NULL)) in intel_enable_shared_dpll()
1902 if (WARN_ON(pll->config.crtc_mask == 0)) in intel_enable_shared_dpll()
1906 pll->name, pll->active, pll->on, in intel_enable_shared_dpll()
1909 if (pll->active++) { in intel_enable_shared_dpll()
1910 WARN_ON(!pll->on); in intel_enable_shared_dpll()
1911 assert_shared_dpll_enabled(dev_priv, pll); in intel_enable_shared_dpll()
1914 WARN_ON(pll->on); in intel_enable_shared_dpll()
1918 DRM_DEBUG_KMS("enabling %s\n", pll->name); in intel_enable_shared_dpll()
1919 pll->enable(dev_priv, pll); in intel_enable_shared_dpll()
1920 pll->on = true; in intel_enable_shared_dpll()
1927 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); in intel_disable_shared_dpll() local
1933 if (pll == NULL) in intel_disable_shared_dpll()
1936 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) in intel_disable_shared_dpll()
1940 pll->name, pll->active, pll->on, in intel_disable_shared_dpll()
1943 if (WARN_ON(pll->active == 0)) { in intel_disable_shared_dpll()
1944 assert_shared_dpll_disabled(dev_priv, pll); in intel_disable_shared_dpll()
1948 assert_shared_dpll_enabled(dev_priv, pll); in intel_disable_shared_dpll()
1949 WARN_ON(!pll->on); in intel_disable_shared_dpll()
1950 if (--pll->active) in intel_disable_shared_dpll()
1953 DRM_DEBUG_KMS("disabling %s\n", pll->name); in intel_disable_shared_dpll()
1954 pll->disable(dev_priv, pll); in intel_disable_shared_dpll()
1955 pll->on = false; in intel_disable_shared_dpll()
4254 struct intel_shared_dpll *pll; in intel_get_shared_dpll() local
4264 pll = &dev_priv->shared_dplls[i]; in intel_get_shared_dpll()
4267 crtc->base.base.id, pll->name); in intel_get_shared_dpll()
4286 pll = &dev_priv->shared_dplls[i]; in intel_get_shared_dpll()
4288 crtc->base.base.id, pll->name); in intel_get_shared_dpll()
4297 pll = &dev_priv->shared_dplls[i]; in intel_get_shared_dpll()
4307 crtc->base.base.id, pll->name, in intel_get_shared_dpll()
4309 pll->active); in intel_get_shared_dpll()
4316 pll = &dev_priv->shared_dplls[i]; in intel_get_shared_dpll()
4319 crtc->base.base.id, pll->name); in intel_get_shared_dpll()
4332 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, in intel_get_shared_dpll()
4337 return pll; in intel_get_shared_dpll()
4344 struct intel_shared_dpll *pll; in intel_shared_dpll_commit() local
4352 pll = &dev_priv->shared_dplls[i]; in intel_shared_dpll_commit()
4353 pll->config = shared_dpll[i]; in intel_shared_dpll_commit()
8919 struct intel_shared_dpll *pll; in ironlake_crtc_compute_clock() local
8961 pll = intel_get_shared_dpll(crtc, crtc_state); in ironlake_crtc_compute_clock()
8962 if (pll == NULL) { in ironlake_crtc_compute_clock()
9299 struct intel_shared_dpll *pll; in ironlake_get_pipe_config() local
9320 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; in ironlake_get_pipe_config()
9322 WARN_ON(!pll->get_hw_state(dev_priv, pll, in ironlake_get_pipe_config()
9808 struct intel_shared_dpll *pll; in haswell_get_ddi_port_state() local
9824 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; in haswell_get_ddi_port_state()
9826 WARN_ON(!pll->get_hw_state(dev_priv, pll, in haswell_get_ddi_port_state()
12830 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in check_shared_dpll_state() local
12836 DRM_DEBUG_KMS("%s\n", pll->name); in check_shared_dpll_state()
12838 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); in check_shared_dpll_state()
12840 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), in check_shared_dpll_state()
12842 pll->active, hweight32(pll->config.crtc_mask)); in check_shared_dpll_state()
12843 I915_STATE_WARN(pll->active && !pll->on, in check_shared_dpll_state()
12845 I915_STATE_WARN(pll->on && !pll->active, in check_shared_dpll_state()
12847 I915_STATE_WARN(pll->on != active, in check_shared_dpll_state()
12849 pll->on, active); in check_shared_dpll_state()
12852 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) in check_shared_dpll_state()
12854 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) in check_shared_dpll_state()
12857 I915_STATE_WARN(pll->active != active_crtcs, in check_shared_dpll_state()
12859 pll->active, active_crtcs); in check_shared_dpll_state()
12860 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, in check_shared_dpll_state()
12862 hweight32(pll->config.crtc_mask), enabled_crtcs); in check_shared_dpll_state()
12864 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, in check_shared_dpll_state()
13339 struct intel_shared_dpll *pll, in ibx_pch_dpll_get_hw_state() argument
13347 val = I915_READ(PCH_DPLL(pll->id)); in ibx_pch_dpll_get_hw_state()
13349 hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); in ibx_pch_dpll_get_hw_state()
13350 hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); in ibx_pch_dpll_get_hw_state()
13356 struct intel_shared_dpll *pll) in ibx_pch_dpll_mode_set() argument
13358 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); in ibx_pch_dpll_mode_set()
13359 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); in ibx_pch_dpll_mode_set()
13363 struct intel_shared_dpll *pll) in ibx_pch_dpll_enable() argument
13368 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); in ibx_pch_dpll_enable()
13371 POSTING_READ(PCH_DPLL(pll->id)); in ibx_pch_dpll_enable()
13379 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); in ibx_pch_dpll_enable()
13380 POSTING_READ(PCH_DPLL(pll->id)); in ibx_pch_dpll_enable()
13385 struct intel_shared_dpll *pll) in ibx_pch_dpll_disable() argument
13392 if (intel_crtc_to_shared_dpll(crtc) == pll) in ibx_pch_dpll_disable()
13396 I915_WRITE(PCH_DPLL(pll->id), 0); in ibx_pch_dpll_disable()
13397 POSTING_READ(PCH_DPLL(pll->id)); in ibx_pch_dpll_disable()
15288 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in intel_modeset_readout_hw_state() local
15290 pll->on = pll->get_hw_state(dev_priv, pll, in intel_modeset_readout_hw_state()
15291 &pll->config.hw_state); in intel_modeset_readout_hw_state()
15292 pll->active = 0; in intel_modeset_readout_hw_state()
15293 pll->config.crtc_mask = 0; in intel_modeset_readout_hw_state()
15295 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { in intel_modeset_readout_hw_state()
15296 pll->active++; in intel_modeset_readout_hw_state()
15297 pll->config.crtc_mask |= 1 << crtc->pipe; in intel_modeset_readout_hw_state()
15302 pll->name, pll->config.crtc_mask, pll->on); in intel_modeset_readout_hw_state()
15304 if (pll->config.crtc_mask) in intel_modeset_readout_hw_state()
15403 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in intel_modeset_setup_hw_state() local
15405 if (!pll->on || pll->active) in intel_modeset_setup_hw_state()
15408 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); in intel_modeset_setup_hw_state()
15410 pll->disable(dev_priv, pll); in intel_modeset_setup_hw_state()
15411 pll->on = false; in intel_modeset_setup_hw_state()