Lines Matching refs:vco
132 intel_range_t dot, vco, n, m, m1, m2, p, p1; member
238 .vco = { .min = 908000, .max = 1512000 },
251 .vco = { .min = 908000, .max = 1512000 },
264 .vco = { .min = 908000, .max = 1512000 },
277 .vco = { .min = 1400000, .max = 2800000 },
290 .vco = { .min = 1400000, .max = 2800000 },
304 .vco = { .min = 1750000, .max = 3500000},
319 .vco = { .min = 1750000, .max = 3500000},
332 .vco = { .min = 1750000, .max = 3500000 },
346 .vco = { .min = 1750000, .max = 3500000 },
360 .vco = { .min = 1700000, .max = 3500000 },
375 .vco = { .min = 1700000, .max = 3500000 },
393 .vco = { .min = 1760000, .max = 3510000 },
406 .vco = { .min = 1760000, .max = 3510000 },
419 .vco = { .min = 1760000, .max = 3510000 },
433 .vco = { .min = 1760000, .max = 3510000 },
446 .vco = { .min = 1760000, .max = 3510000 },
465 .vco = { .min = 4000000, .max = 6000000 },
481 .vco = { .min = 4800000, .max = 6480000 },
492 .vco = { .min = 4800000, .max = 6700000 },
651 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
652 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in pnv_calc_dpll_params()
668 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); in i9xx_calc_dpll_params()
669 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in i9xx_calc_dpll_params()
680 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in vlv_calc_dpll_params()
681 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in vlv_calc_dpll_params()
692 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, in chv_calc_dpll_params()
694 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in chv_calc_dpll_params()
729 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in intel_PLL_is_valid()
5649 unsigned int vco; member
5651 { .freq = 308570, .vco = 8640 },
5652 { .freq = 337500, .vco = 8100 },
5653 { .freq = 432000, .vco = 8640 },
5654 { .freq = 450000, .vco = 8100 },
5655 { .freq = 540000, .vco = 8100 },
5656 { .freq = 617140, .vco = 8640 },
5657 { .freq = 675000, .vco = 8100 },
5673 return e->vco; in skl_cdclk_get_vco()
6969 unsigned int vco; in intel_hpll_vco() local
6988 vco = vco_table[tmp & 0x7]; in intel_hpll_vco()
6989 if (vco == 0) in intel_hpll_vco()
6992 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
6994 return vco; in intel_hpll_vco()
6999 unsigned int cdclk_sel, vco = intel_hpll_vco(dev); in gm45_get_display_clock_speed() local
7006 switch (vco) { in gm45_get_display_clock_speed()
7014 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); in gm45_get_display_clock_speed()
7025 unsigned int cdclk_sel, vco = intel_hpll_vco(dev); in i965gm_get_display_clock_speed() local
7035 switch (vco) { in i965gm_get_display_clock_speed()
7049 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); in i965gm_get_display_clock_speed()
7052 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); in i965gm_get_display_clock_speed()
7063 unsigned int cdclk_sel, vco = intel_hpll_vco(dev); in g33_get_display_clock_speed() local
7073 switch (vco) { in g33_get_display_clock_speed()
7090 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); in g33_get_display_clock_speed()
7093 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); in g33_get_display_clock_speed()
7440 int vco; in chv_prepare_pll() local
7448 vco = pipe_config->dpll.vco; in chv_prepare_pll()
7496 if (vco == 5400000) { in chv_prepare_pll()
7501 } else if (vco <= 6200000) { in chv_prepare_pll()
7506 } else if (vco <= 6480000) { in chv_prepare_pll()