317 	DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",  in vlv_power_sequencer_kick()
417 	DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",  in vlv_power_sequencer_pipe()
503 		DRM_DEBUG_KMS("no initial power sequencer for port %c\n",  in vlv_initial_power_sequencer_setup()
508 	DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",  in vlv_initial_power_sequencer_setup()
643 		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",  in intel_dp_check_edp()
909 		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);  in intel_dp_aux_ch()
1081 	DRM_DEBUG_KMS("registering %s bus for %s\n", name,  in intel_dp_aux_init()
1325 	DRM_DEBUG_KMS("source rates: %s\n", str);  in intel_dp_print_rates()
1329 	DRM_DEBUG_KMS("sink rates: %s\n", str);  in intel_dp_print_rates()
1333 	DRM_DEBUG_KMS("common rates: %s\n", str);  in intel_dp_print_rates()
1437 	DRM_DEBUG_KMS("DP link computation with max lane count %i "  in intel_dp_compute_config()
1450 			DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",  in intel_dp_compute_config()
1510 	DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",  in intel_dp_compute_config()
1513 	DRM_DEBUG_KMS("DP link bw required %i available %i\n",  in intel_dp_compute_config()
1550 	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",  in ironlake_set_pll_cpu_edp()
1559 		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");  in ironlake_set_pll_cpu_edp()
1687 	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",  in wait_panel_status()
1698 	DRM_DEBUG_KMS("Wait complete\n");  in wait_panel_status()
1703 	DRM_DEBUG_KMS("Wait for panel power on\n");  in wait_panel_on()
1709 	DRM_DEBUG_KMS("Wait for panel power off time\n");  in wait_panel_off()
1715 	DRM_DEBUG_KMS("Wait for panel power cycle\n");  in wait_panel_power_cycle()
1787 	DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",  in edp_panel_vdd_on()
1801 	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",  in edp_panel_vdd_on()
1807 		DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",  in edp_panel_vdd_on()
1855 	DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",  in edp_panel_vdd_off_sync()
1868 	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",  in edp_panel_vdd_off_sync()
1940 	DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",  in edp_panel_on()
2002 	DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",  in edp_panel_off()
2075 	DRM_DEBUG_KMS("\n");  in intel_edp_backlight_on()
2114 	DRM_DEBUG_KMS("\n");  in intel_edp_backlight_off()
2137 	DRM_DEBUG_KMS("panel power control backlight %s\n",  in intel_edp_backlight_power()
2157 	DRM_DEBUG_KMS("\n");  in ironlake_edp_pll_on()
2224 		DRM_DEBUG_KMS("failed to %s sink power state\n",  in intel_dp_sink_dpms()
2260 		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",  in intel_dp_get_hw_state()
2353 		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",  in intel_dp_get_config()
2661 	DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",  in vlv_detach_power_sequencer()
2694 		DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",  in vlv_steal_power_sequencer()
2739 	DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",  in vlv_init_panel_power_sequencer()
3513 		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"  in gen6_edp_signal_levels()
3544 		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"  in gen7_edp_signal_levels()
3583 		DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);  in intel_dp_set_signal_levels()
3585 	DRM_DEBUG_KMS("Using vswing level %d\n",  in intel_dp_set_signal_levels()
3587 	DRM_DEBUG_KMS("Using pre-emphasis level %d\n",  in intel_dp_set_signal_levels()
3745 			DRM_DEBUG_KMS("clock recovery OK\n");  in intel_dp_link_training_clock_recovery()
3754 			DRM_DEBUG_KMS("clock recovery not ok, reset");  in intel_dp_link_training_clock_recovery()
3898 		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");  in intel_dp_link_training_channel_equalization()
3931 	DRM_DEBUG_KMS("\n");  in intel_dp_link_down()
3983 	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);  in intel_dp_get_dpcd()
3996 			DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");  in intel_dp_get_dpcd()
4010 			DRM_DEBUG_KMS("PSR2 %s on sink",  in intel_dp_get_dpcd()
4015 	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",  in intel_dp_get_dpcd()
4070 		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",  in intel_dp_probe_oui()
4074 		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",  in intel_dp_probe_oui()
4091 			DRM_DEBUG_KMS("Sink is MST capable\n");  in intel_dp_probe_mst()
4094 			DRM_DEBUG_KMS("Sink is not MST capable\n");  in intel_dp_probe_mst()
4111 		DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");  in intel_dp_sink_crc_stop()
4118 		DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");  in intel_dp_sink_crc_stop()
4212 …DRM_DEBUG_KMS("Unreliable Sink CRC counter: Current returned CRC is identical to the previous one\…  in intel_dp_sink_crc()
4277 			DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",  in intel_dp_autotest_edid()
4293 			DRM_DEBUG_KMS("Failed to write EDID checksum\n");  in intel_dp_autotest_edid()
4326 		DRM_DEBUG_KMS("Could not read test request from sink\n");  in intel_dp_handle_test_request()
4332 		DRM_DEBUG_KMS("LINK_TRAINING test requested\n");  in intel_dp_handle_test_request()
4337 		DRM_DEBUG_KMS("TEST_PATTERN test requested\n");  in intel_dp_handle_test_request()
4342 		DRM_DEBUG_KMS("EDID test requested\n");  in intel_dp_handle_test_request()
4347 		DRM_DEBUG_KMS("PHY_PATTERN test requested\n");  in intel_dp_handle_test_request()
4352 		DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);  in intel_dp_handle_test_request()
4361 		DRM_DEBUG_KMS("Could not write test response to sink\n");  in intel_dp_handle_test_request()
4381 				DRM_DEBUG_KMS("channel EQ not ok, retraining\n");  in intel_dp_check_mst_status()
4386 			DRM_DEBUG_KMS("got esi %3ph\n", esi);  in intel_dp_check_mst_status()
4402 					DRM_DEBUG_KMS("got esi2 %3ph\n", esi);  in intel_dp_check_mst_status()
4411 			DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");  in intel_dp_check_mst_status()
4470 		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",  in intel_dp_check_link_status()
4523 	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");  in intel_dp_detect_dpcd()
4777 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",  in intel_dp_detect()
4846 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",  in intel_dp_force()
4971 			DRM_DEBUG_KMS("no scaling not supported\n");  in intel_dp_set_property()
5073 	DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");  in intel_edp_panel_vdd_sanitize()
5147 		DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",  in intel_dp_hpd_pulse()
5152 	DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",  in intel_dp_hpd_pulse()
5197 …DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.ms…  in intel_dp_hpd_pulse()
5364 	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",  in intel_dp_init_panel_power_sequencer()
5381 	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",  in intel_dp_init_panel_power_sequencer()
5404 	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",  in intel_dp_init_panel_power_sequencer()
5408 	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",  in intel_dp_init_panel_power_sequencer()
5492 	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",  in intel_dp_init_panel_power_sequencer_registers()
5523 		DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");  in intel_dp_set_drrs_state()
5528 		DRM_DEBUG_KMS("DRRS not supported.\n");  in intel_dp_set_drrs_state()
5542 		DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");  in intel_dp_set_drrs_state()
5549 		DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");  in intel_dp_set_drrs_state()
5558 		DRM_DEBUG_KMS(  in intel_dp_set_drrs_state()
5564 		DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");  in intel_dp_set_drrs_state()
5601 	DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);  in intel_dp_set_drrs_state()
5619 		DRM_DEBUG_KMS("Panel doesn't support DRRS\n");  in intel_edp_drrs_enable()
5858 		DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");  in intel_dp_drrs_init()
5863 		DRM_DEBUG_KMS("VBT doesn't support DRRS\n");  in intel_dp_drrs_init()
5871 		DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");  in intel_dp_drrs_init()
5878 	DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");  in intel_dp_drrs_init()
5978 		DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",  in intel_edp_init_connector()
6042 	DRM_DEBUG_KMS("Adding %s connector on port %c\n",  in intel_dp_init_connector()