Lines Matching refs:I915_READ
312 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, in vlv_power_sequencer_kick()
323 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; in vlv_power_sequencer_kick()
333 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
440 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; in vlv_pipe_has_pp_on()
446 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; in vlv_pipe_has_vdd_on()
463 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & in vlv_initial_pps_pipe()
590 pp_div = I915_READ(pp_div_reg); in edp_notify_handler()
615 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; in edp_have_panel_power()
629 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; in edp_have_panel_vdd()
644 I915_READ(_pp_stat_reg(intel_dp)), in intel_dp_check_edp()
645 I915_READ(_pp_ctrl_reg(intel_dp))); in intel_dp_check_edp()
829 const u32 status = I915_READ(ch_ctl); in intel_dp_aux_ch()
921 intel_dp_unpack_aux(I915_READ(ch_data + i), in intel_dp_aux_ch()
1552 dpa_ctl = I915_READ(DP_A); in ironlake_set_pll_cpu_edp()
1611 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; in intel_dp_prepare()
1638 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); in intel_dp_prepare()
1689 I915_READ(pp_stat_reg), in wait_panel_status()
1690 I915_READ(pp_ctrl_reg)); in wait_panel_status()
1692 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { in wait_panel_status()
1694 I915_READ(pp_stat_reg), in wait_panel_status()
1695 I915_READ(pp_ctrl_reg)); in wait_panel_status()
1749 control = I915_READ(_pp_ctrl_reg(intel_dp)); in ironlake_get_pp_control()
1802 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); in edp_panel_vdd_on()
1869 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); in edp_panel_vdd_off_sync()
2158 dpa_ctl = I915_READ(DP_A); in ironlake_edp_pll_on()
2183 dpa_ctl = I915_READ(DP_A); in ironlake_edp_pll_off()
2242 tmp = I915_READ(intel_dp->output_reg); in intel_dp_get_hw_state()
2253 u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); in intel_dp_get_hw_state()
2282 tmp = I915_READ(intel_dp->output_reg); in intel_dp_get_config()
2287 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); in intel_dp_get_config()
2324 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) in intel_dp_get_config()
2471 uint32_t temp = I915_READ(DP_TP_CTL(port)); in _intel_dp_set_link_train()
2574 uint32_t dp_reg = I915_READ(intel_dp->output_reg); in intel_enable_dp()
3669 val = I915_READ(DP_TP_CTL(port)); in intel_dp_set_idle_link_train()
3684 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), in intel_dp_set_idle_link_train()
3928 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) in intel_dp_link_down()
4562 return I915_READ(SDEISR) & bit; in ibx_digital_port_connected()
4590 return I915_READ(SDEISR) & bit; in cpt_digital_port_connected()
4613 return I915_READ(PORT_HOTPLUG_STAT) & bit; in g4x_digital_port_connected()
4636 return I915_READ(PORT_HOTPLUG_STAT) & bit; in vlv_digital_port_connected()
4662 return I915_READ(GEN8_DE_PORT_ISR) & bit; in bxt_digital_port_connected()
5332 pp_on = I915_READ(pp_on_reg); in intel_dp_init_panel_power_sequencer()
5333 pp_off = I915_READ(pp_off_reg); in intel_dp_init_panel_power_sequencer()
5336 pp_div = I915_READ(pp_div_reg); in intel_dp_init_panel_power_sequencer()
5462 pp_div = I915_READ(pp_ctrl_reg); in intel_dp_init_panel_power_sequencer_registers()
5493 I915_READ(pp_on_reg), in intel_dp_init_panel_power_sequencer_registers()
5494 I915_READ(pp_off_reg), in intel_dp_init_panel_power_sequencer_registers()
5496 (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) : in intel_dp_init_panel_power_sequencer_registers()
5497 I915_READ(pp_div_reg)); in intel_dp_init_panel_power_sequencer_registers()
5584 val = I915_READ(reg); in intel_dp_set_drrs_state()
6021 intel_dp->DP = I915_READ(intel_dp->output_reg); in intel_dp_init_connector()
6129 u32 temp = I915_READ(PEG_BAND_GAP_DATA); in intel_dp_init_connector()