133 static unsigned int intel_dp_unused_lane_mask(int lane_count)  in intel_dp_unused_lane_mask()  argument
135 	return ~((1 << lane_count) - 1) & 0xf;  in intel_dp_unused_lane_mask()
1389 	int lane_count, clock;  in intel_dp_compute_config()  local
1471 			for (lane_count = min_lane_count;  in intel_dp_compute_config()
1472 				lane_count <= max_lane_count;  in intel_dp_compute_config()
1473 				lane_count <<= 1) {  in intel_dp_compute_config()
1477 								    lane_count);  in intel_dp_compute_config()
1502 	pipe_config->lane_count = lane_count;  in intel_dp_compute_config()
1511 		      link_bw, rate_select, pipe_config->lane_count,  in intel_dp_compute_config()
1516 	intel_link_compute_m_n(bpp, lane_count,  in intel_dp_compute_config()
1524 			intel_link_compute_m_n(bpp, lane_count,  in intel_dp_compute_config()
1577 	intel_dp->lane_count = pipe_config->lane_count;  in intel_dp_set_link_params()
1615 	intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);  in intel_dp_prepare()
2318 	pipe_config->lane_count =  in intel_dp_get_config()
2416 	if (crtc->config->lane_count > 2) {  in chv_data_lane_soft_reset()
2433 	if (crtc->config->lane_count > 2) {  in chv_data_lane_soft_reset()
2596 			lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);  in intel_enable_dp()
2826 	if (intel_crtc->config->lane_count > 2) {  in chv_pre_enable_dp()
2833 	for (i = 0; i < intel_crtc->config->lane_count; i++) {  in chv_pre_enable_dp()
2835 		if (intel_crtc->config->lane_count == 1)  in chv_pre_enable_dp()
2859 	if (intel_crtc->config->lane_count > 2) {  in chv_pre_enable_dp()
2872 	if (intel_crtc->config->lane_count > 2) {  in chv_pre_enable_dp()
2905 		intel_dp_unused_lane_mask(intel_crtc->config->lane_count);  in chv_dp_pre_pll_enable()
2953 	if (intel_crtc->config->lane_count > 2) {  in chv_dp_pre_pll_enable()
3344 	if (intel_crtc->config->lane_count > 2) {  in chv_signal_levels()
3357 	if (intel_crtc->config->lane_count > 2) {  in chv_signal_levels()
3365 	for (i = 0; i < intel_crtc->config->lane_count; i++) {  in chv_signal_levels()
3373 	for (i = 0; i < intel_crtc->config->lane_count; i++) {  in chv_signal_levels()
3396 	for (i = 0; i < intel_crtc->config->lane_count; i++) {  in chv_signal_levels()
3410 	if (intel_crtc->config->lane_count > 2) {  in chv_signal_levels()
3431 	for (lane = 0; lane < intel_dp->lane_count; lane++) {  in intel_get_adjust_train()
3617 		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);  in intel_dp_set_link_train()
3618 		len = intel_dp->lane_count + 1;  in intel_dp_set_link_train()
3653 				intel_dp->train_set, intel_dp->lane_count);  in intel_dp_update_link_train()
3655 	return ret == intel_dp->lane_count;  in intel_dp_update_link_train()
3710 	link_config[1] = intel_dp->lane_count;  in intel_dp_link_training_clock_recovery()
3744 		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {  in intel_dp_link_training_clock_recovery()
3767 		for (i = 0; i < intel_dp->lane_count; i++)  in intel_dp_link_training_clock_recovery()
3770 		if (i == intel_dp->lane_count) {  in intel_dp_link_training_clock_recovery()
3856 					      intel_dp->lane_count)) {  in intel_dp_link_training_channel_equalization()
3867 					 intel_dp->lane_count)) {  in intel_dp_link_training_channel_equalization()
4380 			    !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {  in intel_dp_check_mst_status()
4469 	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {  in intel_dp_check_link_status()