55 	WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,  in assert_hdmi_port_disabled()
141 	u32 val = I915_READ(VIDEO_DIP_CTL);  in g4x_write_infoframe()
176 	u32 val = I915_READ(VIDEO_DIP_CTL);  in g4x_infoframe_enabled()
197 	u32 val = I915_READ(reg);  in ibx_write_infoframe()
233 	u32 val = I915_READ(reg);  in ibx_infoframe_enabled()
255 	u32 val = I915_READ(reg);  in cpt_write_infoframe()
293 	u32 val = I915_READ(reg);  in cpt_infoframe_enabled()
312 	u32 val = I915_READ(reg);  in vlv_write_infoframe()
348 	u32 val = I915_READ(reg);  in vlv_infoframe_enabled()
373 	u32 val = I915_READ(ctl_reg);  in hsw_write_infoframe()
405 	u32 val = I915_READ(ctl_reg);  in hsw_infoframe_enabled()
517 	u32 val = I915_READ(reg);  in g4x_set_infoframes()
670 	u32 val = I915_READ(reg);  in ibx_set_infoframes()
721 	u32 val = I915_READ(reg);  in cpt_set_infoframes()
764 	u32 val = I915_READ(reg);  in vlv_set_infoframes()
815 	u32 val = I915_READ(reg);  in hsw_set_infoframes()
889 	tmp = I915_READ(intel_hdmi->hdmi_reg);  in intel_hdmi_get_hw_state()
913 	tmp = I915_READ(intel_hdmi->hdmi_reg);  in intel_hdmi_get_config()
972 	temp = I915_READ(intel_hdmi->hdmi_reg);  in g4x_enable_hdmi()
993 	temp = I915_READ(intel_hdmi->hdmi_reg);  in ibx_enable_hdmi()
1043 	temp = I915_READ(intel_hdmi->hdmi_reg);  in cpt_enable_hdmi()
1061 			   I915_READ(TRANS_CHICKEN1(pipe)) |  in cpt_enable_hdmi()
1079 			   I915_READ(TRANS_CHICKEN1(pipe)) &  in cpt_enable_hdmi()
1099 	temp = I915_READ(intel_hdmi->hdmi_reg);  in intel_disable_hdmi()
2138 		u32 temp = I915_READ(PEG_BAND_GAP_DATA);  in intel_hdmi_init_connector()