571 	entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);  in intel_calculate_wm()
713 	entries = DIV_ROUND_UP(entries, display->cacheline_size);  in g4x_compute_wm0()
725 	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);  in g4x_compute_wm0()
803 	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);  in g4x_compute_srwm()
808 	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);  in g4x_compute_srwm()
906 	ret = DIV_ROUND_UP(ret, 64);  in vlv_wm_method2()
1007 	fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);  in vlv_compute_fifo()
1441 		entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);  in i965_update_wm()
1451 		entries = DIV_ROUND_UP(entries,  in i965_update_wm()
1588 		entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);  in i9xx_update_wm()
1701 	ret = DIV_ROUND_UP(ret, 64) + 2;  in ilk_wm_method2()
1708 	return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;  in ilk_wm_fbc()
2220 		wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));  in ilk_increase_wm_latency()
3004 	ret = DIV_ROUND_UP(wm_intermediate_val, 1000);  in skl_wm_method1()
3025 		plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);  in skl_wm_method2()
3028 		plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);  in skl_wm_method2()
3032 	ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *  in skl_wm_method2()
3166 	plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);  in skl_compute_plane_wm()
3194 	res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);  in skl_compute_plane_wm()
3252 	return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);  in skl_compute_linetime_wm()