235 	DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");  in intel_get_cxsr_latency()
312 	DRM_DEBUG_KMS("memory self-refresh is %s\n",  in intel_set_memory_cxsr()
380 	DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",  in vlv_get_fifo_size()
398 	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,  in i9xx_get_fifo_size()
415 	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,  in i830_get_fifo_size()
430 	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,  in i845_get_fifo_size()
573 	DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);  in intel_calculate_wm()
577 	DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);  in intel_calculate_wm()
625 		DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");  in pineview_update_wm()
644 		DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);  in pineview_update_wm()
672 		DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);  in pineview_update_wm()
745 	DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",  in g4x_check_srwm()
749 		DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",  in g4x_check_srwm()
755 		DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",  in g4x_check_srwm()
761 		DRM_DEBUG_KMS("SR latency is 0, disabling\n");  in g4x_check_srwm()
1191 	DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",  in vlv_pipe_set_fifo_size()
1334 	DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "  in vlv_update_wm()
1391 	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "  in g4x_update_wm()
1446 		DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",  in i965_update_wm()
1459 		DRM_DEBUG_KMS("self-refresh watermark: display plane %d "  in i965_update_wm()
1469 	DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",  in i965_update_wm()
1551 	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);  in i9xx_update_wm()
1589 		DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);  in i9xx_update_wm()
1601 	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",  in i9xx_update_wm()
1639 	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);  in i845_update_wm()
1960 			DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",  in ilk_validate_wm_level()
1963 			DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",  in ilk_validate_wm_level()
1966 			DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",  in ilk_validate_wm_level()
2204 		DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",  in intel_print_wm_latency()
2241 	DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");  in snb_wm_latency_quirk()
3429 	DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);  in skl_wm_flush_pipe()
4046 			DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "  in vlv_wm_get_hw_state()
4059 		DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",  in vlv_wm_get_hw_state()
4063 	DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",  in vlv_wm_get_hw_state()
4624 		DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",  in intel_print_rc6_info()
4630 		DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",  in intel_print_rc6_info()
4651 			DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",  in sanitize_rc6_option()
6433 		DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",  in gen6_check_mch_setup()
7079 			DRM_DEBUG_KMS("Failed to read display plane latency. "  in intel_init_pm()