60 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |  in bxt_init_clock_gating()
67 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |  in bxt_init_clock_gating()
76 	tmp = I915_READ(CLKCFG);  in i915_pineview_get_mem_freq()
106 	tmp = I915_READ(CSHRDDR3CTL);  in i915_pineview_get_mem_freq()
294 		val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;  in intel_set_memory_cxsr()
345 		dsparb = I915_READ(DSPARB);  in vlv_get_fifo_size()
346 		dsparb2 = I915_READ(DSPARB2);  in vlv_get_fifo_size()
351 		dsparb = I915_READ(DSPARB);  in vlv_get_fifo_size()
352 		dsparb2 = I915_READ(DSPARB2);  in vlv_get_fifo_size()
357 		dsparb2 = I915_READ(DSPARB2);  in vlv_get_fifo_size()
358 		dsparb3 = I915_READ(DSPARB3);  in vlv_get_fifo_size()
391 	uint32_t dsparb = I915_READ(DSPARB);  in i9xx_get_fifo_size()
407 	uint32_t dsparb = I915_READ(DSPARB);  in i830_get_fifo_size()
424 	uint32_t dsparb = I915_READ(DSPARB);  in i845_get_fifo_size()
640 		reg = I915_READ(DSPFW1);  in pineview_update_wm()
650 		reg = I915_READ(DSPFW3);  in pineview_update_wm()
659 		reg = I915_READ(DSPFW3);  in pineview_update_wm()
668 		reg = I915_READ(DSPFW3);  in pineview_update_wm()
1198 		dsparb = I915_READ(DSPARB);  in vlv_pipe_set_fifo_size()
1199 		dsparb2 = I915_READ(DSPARB2);  in vlv_pipe_set_fifo_size()
1215 		dsparb = I915_READ(DSPARB);  in vlv_pipe_set_fifo_size()
1216 		dsparb2 = I915_READ(DSPARB2);  in vlv_pipe_set_fifo_size()
1232 		dsparb3 = I915_READ(DSPARB3);  in vlv_pipe_set_fifo_size()
1233 		dsparb2 = I915_READ(DSPARB2);  in vlv_pipe_set_fifo_size()
1403 		   (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |  in g4x_update_wm()
1407 		   (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |  in g4x_update_wm()
1636 	fwater_lo = I915_READ(FW_BLC) & ~0xfff;  in i845_update_wm()
2133 		uint32_t sskpd = I915_READ(MCH_SSKPD);  in intel_read_wm_latency()
2140 		uint32_t mltr = I915_READ(MLTR_ILK);  in intel_read_wm_latency()
2697 			val = I915_READ(WM_MISC);  in ilk_write_wm_values()
2704 			val = I915_READ(DISP_ARB_CTL2);  in ilk_write_wm_values()
2714 		val = I915_READ(DISP_ARB_CTL);  in ilk_write_wm_values()
2828 			val = I915_READ(PLANE_BUF_CFG(pipe, plane));  in skl_ddb_get_hw_state()
2833 		val = I915_READ(CUR_BUF_CFG(pipe));  in skl_ddb_get_hw_state()
3433 			   I915_READ(PLANE_SURF(pipe, plane)));  in skl_wm_flush_pipe()
3435 	I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));  in skl_wm_flush_pipe()
3815 	hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));  in skl_pipe_wm_get_hw_state()
3820 					I915_READ(PLANE_WM(pipe, i, level));  in skl_pipe_wm_get_hw_state()
3821 		hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));  in skl_pipe_wm_get_hw_state()
3825 		hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));  in skl_pipe_wm_get_hw_state()
3826 	hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));  in skl_pipe_wm_get_hw_state()
3879 	hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);  in ilk_pipe_wm_get_hw_state()
3881 		hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));  in ilk_pipe_wm_get_hw_state()
3926 		tmp = I915_READ(VLV_DDL(pipe));  in vlv_read_wm_values()
3938 	tmp = I915_READ(DSPFW1);  in vlv_read_wm_values()
3944 	tmp = I915_READ(DSPFW2);  in vlv_read_wm_values()
3949 	tmp = I915_READ(DSPFW3);  in vlv_read_wm_values()
3953 		tmp = I915_READ(DSPFW7_CHV);  in vlv_read_wm_values()
3957 		tmp = I915_READ(DSPFW8_CHV);  in vlv_read_wm_values()
3961 		tmp = I915_READ(DSPFW9_CHV);  in vlv_read_wm_values()
3965 		tmp = I915_READ(DSPHOWM);  in vlv_read_wm_values()
3977 		tmp = I915_READ(DSPFW7);  in vlv_read_wm_values()
3981 		tmp = I915_READ(DSPHOWM);  in vlv_read_wm_values()
4021 	wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;  in vlv_wm_get_hw_state()
4076 	hw->wm_lp[0] = I915_READ(WM1_LP_ILK);  in ilk_wm_get_hw_state()
4077 	hw->wm_lp[1] = I915_READ(WM2_LP_ILK);  in ilk_wm_get_hw_state()
4078 	hw->wm_lp[2] = I915_READ(WM3_LP_ILK);  in ilk_wm_get_hw_state()
4080 	hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);  in ilk_wm_get_hw_state()
4082 		hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);  in ilk_wm_get_hw_state()
4083 		hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);  in ilk_wm_get_hw_state()
4087 		hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?  in ilk_wm_get_hw_state()
4090 		hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?  in ilk_wm_get_hw_state()
4094 		!(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);  in ilk_wm_get_hw_state()
4188 	u32 rgvmodectl = I915_READ(MEMMODECTL);  in ironlake_enable_drps()
4194 	I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);  in ironlake_enable_drps()
4195 	I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);  in ironlake_enable_drps()
4213 	vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>  in ironlake_enable_drps()
4238 	if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))  in ironlake_enable_drps()
4244 	dev_priv->ips.last_count1 = I915_READ(DMIEC) +  in ironlake_enable_drps()
4245 		I915_READ(DDREC) + I915_READ(CSIEC);  in ironlake_enable_drps()
4247 	dev_priv->ips.last_count2 = I915_READ(GFXEC);  in ironlake_enable_drps()
4263 	I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);  in ironlake_disable_drps()
4265 	I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);  in ironlake_disable_drps()
4267 	I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);  in ironlake_disable_drps()
4679 		rp_state_cap = I915_READ(BXT_RP_STATE_CAP);  in gen6_init_rps_frequencies()
4684 		rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);  in gen6_init_rps_frequencies()
4941 	if ((gtfifodbg = I915_READ(GTFIFODBG))) {  in gen6_enable_rps()
5056 	min_ring_freq = I915_READ(DCLK) & 0xf;  in __gen6_update_ring_freq()
5219 	unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;  in valleyview_check_pctx()
5229 	unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;  in cherryview_check_pctx()
5244 	pcbr = I915_READ(VLV_PCBR);  in cherryview_setup_pctx()
5254 	DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));  in cherryview_setup_pctx()
5267 	pcbr = I915_READ(VLV_PCBR);  in valleyview_setup_pctx()
5300 	DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));  in valleyview_setup_pctx()
5449 	gtfifodbg = I915_READ(GTFIFODBG);  in cherryview_enable_rps()
5484 	pcbr = I915_READ(VLV_PCBR);  in cherryview_enable_rps()
5549 	if ((gtfifodbg = I915_READ(GTFIFODBG))) {  in valleyview_enable_rps()
5676 	count1 = I915_READ(DMIEC);  in __i915_chipset_val()
5677 	count2 = I915_READ(DDREC);  in __i915_chipset_val()
5678 	count3 = I915_READ(CSIEC);  in __i915_chipset_val()
5733 	tsfs = I915_READ(TSFS);  in i915_mch_val()
5781 	count = I915_READ(GFXEC);  in __i915_update_gfx_val()
5820 	pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));  in __i915_gfx_val()
6069 		u32 pxvidfreq = I915_READ(PXVFREQ(i));  in intel_init_emon()
6111 	lcfuse = I915_READ(LCFUSE02);  in intel_init_emon()
6293 			   I915_READ(DSPCNTR(pipe)) |  in g4x_disable_trickle_feed()
6296 		I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));  in g4x_disable_trickle_feed()
6305 	I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);  in ilk_init_lp_watermarks()
6306 	I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);  in ilk_init_lp_watermarks()
6307 	I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);  in ilk_init_lp_watermarks()
6342 		   (I915_READ(ILK_DISPLAY_CHICKEN2) |  in ironlake_init_clock_gating()
6346 		   (I915_READ(DISP_ARB_CTL) |  in ironlake_init_clock_gating()
6361 			   I915_READ(ILK_DISPLAY_CHICKEN1) |  in ironlake_init_clock_gating()
6364 			   I915_READ(ILK_DISPLAY_CHICKEN2) |  in ironlake_init_clock_gating()
6371 		   I915_READ(ILK_DISPLAY_CHICKEN2) |  in ironlake_init_clock_gating()
6403 	I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |  in cpt_init_clock_gating()
6409 		val = I915_READ(TRANS_CHICKEN2(pipe));  in cpt_init_clock_gating()
6431 	tmp = I915_READ(MCH_SSKPD);  in gen6_check_mch_setup()
6445 		   I915_READ(ILK_DISPLAY_CHICKEN2) |  in gen6_init_clock_gating()
6472 		   I915_READ(GEN6_UCGCTL1) |  in gen6_init_clock_gating()
6517 		   I915_READ(ILK_DISPLAY_CHICKEN1) |  in gen6_init_clock_gating()
6520 		   I915_READ(ILK_DISPLAY_CHICKEN2) |  in gen6_init_clock_gating()
6523 		   I915_READ(ILK_DSPCLK_GATE_D) |  in gen6_init_clock_gating()
6536 	uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);  in gen7_setup_fixed_func_scheduler()
6562 			   I915_READ(SOUTH_DSPCLK_GATE_D) |  in lpt_init_clock_gating()
6567 		   I915_READ(TRANS_CHICKEN1(PIPE_A)) |  in lpt_init_clock_gating()
6576 		uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);  in lpt_suspend_hw()
6592 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);  in broadwell_init_clock_gating()
6596 		   I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);  in broadwell_init_clock_gating()
6601 			   I915_READ(CHICKEN_PIPESL_1(pipe)) |  in broadwell_init_clock_gating()
6608 		   I915_READ(GEN7_FF_THREAD_MODE) &  in broadwell_init_clock_gating()
6615 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |  in broadwell_init_clock_gating()
6622 	misccpctl = I915_READ(GEN7_MISCCPCTL);  in broadwell_init_clock_gating()
6656 			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |  in haswell_init_clock_gating()
6661 		   I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);  in haswell_init_clock_gating()
6690 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);  in haswell_init_clock_gating()
6694 		   I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);  in haswell_init_clock_gating()
6746 	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &  in ivybridge_init_clock_gating()
6758 			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |  in ivybridge_init_clock_gating()
6786 	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);  in ivybridge_init_clock_gating()
6833 	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &  in valleyview_init_clock_gating()
6842 		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |  in valleyview_init_clock_gating()
6858 		   I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);  in valleyview_init_clock_gating()
6901 		   I915_READ(GEN7_FF_THREAD_MODE) &  in cherryview_init_clock_gating()
6909 	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |  in cherryview_init_clock_gating()
6913 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |  in cherryview_init_clock_gating()
6986 	u32 dstate = I915_READ(D_STATE);  in gen3_init_clock_gating()
7156 	if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {  in sandybridge_pcode_read()
7165 	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,  in sandybridge_pcode_read()
7171 	*val = I915_READ(GEN6_PCODE_DATA);  in sandybridge_pcode_read()
7181 	if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {  in sandybridge_pcode_write()
7189 	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,  in sandybridge_pcode_write()