Lines Matching refs:I915_WRITE
60 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
67 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
287 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); in intel_set_memory_cxsr()
291 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); in intel_set_memory_cxsr()
296 I915_WRITE(DSPFW3, val); in intel_set_memory_cxsr()
301 I915_WRITE(FW_BLC_SELF, val); in intel_set_memory_cxsr()
306 I915_WRITE(INSTPM, val); in intel_set_memory_cxsr()
643 I915_WRITE(DSPFW1, reg); in pineview_update_wm()
653 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
662 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
671 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
825 I915_WRITE(VLV_DDL(pipe), in vlv_write_wm_values()
831 I915_WRITE(DSPFW1, in vlv_write_wm_values()
836 I915_WRITE(DSPFW2, in vlv_write_wm_values()
840 I915_WRITE(DSPFW3, in vlv_write_wm_values()
844 I915_WRITE(DSPFW7_CHV, in vlv_write_wm_values()
847 I915_WRITE(DSPFW8_CHV, in vlv_write_wm_values()
850 I915_WRITE(DSPFW9_CHV, in vlv_write_wm_values()
853 I915_WRITE(DSPHOWM, in vlv_write_wm_values()
865 I915_WRITE(DSPFW7, in vlv_write_wm_values()
868 I915_WRITE(DSPHOWM, in vlv_write_wm_values()
879 I915_WRITE(DSPFW4, 0); in vlv_write_wm_values()
880 I915_WRITE(DSPFW5, 0); in vlv_write_wm_values()
881 I915_WRITE(DSPFW6, 0); in vlv_write_wm_values()
882 I915_WRITE(DSPHOWM1, 0); in vlv_write_wm_values()
1211 I915_WRITE(DSPARB, dsparb); in vlv_pipe_set_fifo_size()
1212 I915_WRITE(DSPARB2, dsparb2); in vlv_pipe_set_fifo_size()
1228 I915_WRITE(DSPARB, dsparb); in vlv_pipe_set_fifo_size()
1229 I915_WRITE(DSPARB2, dsparb2); in vlv_pipe_set_fifo_size()
1245 I915_WRITE(DSPARB3, dsparb3); in vlv_pipe_set_fifo_size()
1246 I915_WRITE(DSPARB2, dsparb2); in vlv_pipe_set_fifo_size()
1397 I915_WRITE(DSPFW1, in g4x_update_wm()
1402 I915_WRITE(DSPFW2, in g4x_update_wm()
1406 I915_WRITE(DSPFW3, in g4x_update_wm()
1473 I915_WRITE(DSPFW1, FW_WM(srwm, SR) | in i965_update_wm()
1477 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | in i965_update_wm()
1480 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); in i965_update_wm()
1595 I915_WRITE(FW_BLC_SELF, in i9xx_update_wm()
1598 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); in i9xx_update_wm()
1611 I915_WRITE(FW_BLC, fwater_lo); in i9xx_update_wm()
1612 I915_WRITE(FW_BLC2, fwater_hi); in i9xx_update_wm()
1641 I915_WRITE(FW_BLC, fwater_lo); in i845_update_wm()
2641 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); in _ilk_disable_lp_wm()
2646 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); in _ilk_disable_lp_wm()
2651 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); in _ilk_disable_lp_wm()
2682 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); in ilk_write_wm_values()
2684 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); in ilk_write_wm_values()
2686 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); in ilk_write_wm_values()
2689 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); in ilk_write_wm_values()
2691 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); in ilk_write_wm_values()
2693 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); in ilk_write_wm_values()
2702 I915_WRITE(WM_MISC, val); in ilk_write_wm_values()
2709 I915_WRITE(DISP_ARB_CTL2, val); in ilk_write_wm_values()
2719 I915_WRITE(DISP_ARB_CTL, val); in ilk_write_wm_values()
2724 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); in ilk_write_wm_values()
2728 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); in ilk_write_wm_values()
2730 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); in ilk_write_wm_values()
2734 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); in ilk_write_wm_values()
2736 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); in ilk_write_wm_values()
2738 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); in ilk_write_wm_values()
3353 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); in skl_ddb_entry_write()
3355 I915_WRITE(reg, 0); in skl_ddb_entry_write()
3371 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); in skl_write_wm_values()
3375 I915_WRITE(PLANE_WM(pipe, i, level), in skl_write_wm_values()
3377 I915_WRITE(CUR_WM(pipe, level), in skl_write_wm_values()
3381 I915_WRITE(PLANE_WM_TRANS(pipe, i), in skl_write_wm_values()
3383 I915_WRITE(CUR_WM_TRANS(pipe), in skl_write_wm_values()
3432 I915_WRITE(PLANE_SURF(pipe, plane), in skl_wm_flush_pipe()
3435 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); in skl_wm_flush_pipe()
4198 I915_WRITE(RCUPEI, 100000); in ironlake_enable_drps()
4199 I915_WRITE(RCDNEI, 100000); in ironlake_enable_drps()
4202 I915_WRITE(RCBMAXAVG, 90000); in ironlake_enable_drps()
4203 I915_WRITE(RCBMINAVG, 80000); in ironlake_enable_drps()
4205 I915_WRITE(MEMIHYST, 1); in ironlake_enable_drps()
4226 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); in ironlake_enable_drps()
4232 I915_WRITE(VIDSTART, vstart); in ironlake_enable_drps()
4236 I915_WRITE(MEMMODECTL, rgvmodectl); in ironlake_enable_drps()
4263 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); in ironlake_disable_drps()
4264 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); in ironlake_disable_drps()
4265 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); in ironlake_disable_drps()
4266 I915_WRITE(DEIIR, DE_PCU_EVENT); in ironlake_disable_drps()
4267 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); in ironlake_disable_drps()
4273 I915_WRITE(MEMSWCTL, rgvswctl); in ironlake_disable_drps()
4373 I915_WRITE(GEN6_RP_UP_EI, in gen6_set_rps_thresholds()
4375 I915_WRITE(GEN6_RP_UP_THRESHOLD, in gen6_set_rps_thresholds()
4378 I915_WRITE(GEN6_RP_DOWN_EI, in gen6_set_rps_thresholds()
4380 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, in gen6_set_rps_thresholds()
4383 I915_WRITE(GEN6_RP_CONTROL, in gen6_set_rps_thresholds()
4433 I915_WRITE(GEN6_RPNSWREQ, in gen6_set_rps()
4436 I915_WRITE(GEN6_RPNSWREQ, in gen6_set_rps()
4439 I915_WRITE(GEN6_RPNSWREQ, in gen6_set_rps()
4448 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); in gen6_set_rps()
4449 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); in gen6_set_rps()
4469 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); in valleyview_set_rps()
4508 I915_WRITE(GEN6_PMINTRMSK, in gen6_rps_busy()
4525 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); in gen6_rps_idle()
4583 I915_WRITE(GEN6_RC_CONTROL, 0); in gen9_disable_rps()
4584 I915_WRITE(GEN9_PG_ENABLE, 0); in gen9_disable_rps()
4591 I915_WRITE(GEN6_RC_CONTROL, 0); in gen6_disable_rps()
4592 I915_WRITE(GEN6_RPNSWREQ, 1 << 31); in gen6_disable_rps()
4599 I915_WRITE(GEN6_RC_CONTROL, 0); in cherryview_disable_rps()
4610 I915_WRITE(GEN6_RC_CONTROL, 0); in valleyview_disable_rps()
4749 I915_WRITE(GEN6_RC_VIDEO_FREQ, in gen9_enable_rps()
4753 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, in gen9_enable_rps()
4756 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); in gen9_enable_rps()
4775 I915_WRITE(GEN6_RC_STATE, 0); in gen9_enable_rc6()
4782 I915_WRITE(GEN6_RC_CONTROL, 0); in gen9_enable_rc6()
4788 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); in gen9_enable_rc6()
4790 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); in gen9_enable_rc6()
4791 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen9_enable_rc6()
4792 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen9_enable_rc6()
4794 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); in gen9_enable_rc6()
4797 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); in gen9_enable_rc6()
4799 I915_WRITE(GEN6_RC_SLEEP, 0); in gen9_enable_rc6()
4802 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); in gen9_enable_rc6()
4803 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); in gen9_enable_rc6()
4813 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ in gen9_enable_rc6()
4814 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | in gen9_enable_rc6()
4818 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ in gen9_enable_rc6()
4819 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | in gen9_enable_rc6()
4830 I915_WRITE(GEN9_PG_ENABLE, 0); in gen9_enable_rc6()
4832 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? in gen9_enable_rc6()
4847 I915_WRITE(GEN6_RC_STATE, 0); in gen8_enable_rps()
4854 I915_WRITE(GEN6_RC_CONTROL, 0); in gen8_enable_rps()
4860 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); in gen8_enable_rps()
4861 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen8_enable_rps()
4862 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen8_enable_rps()
4864 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); in gen8_enable_rps()
4865 I915_WRITE(GEN6_RC_SLEEP, 0); in gen8_enable_rps()
4867 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ in gen8_enable_rps()
4869 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ in gen8_enable_rps()
4876 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | in gen8_enable_rps()
4880 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | in gen8_enable_rps()
4885 I915_WRITE(GEN6_RPNSWREQ, in gen8_enable_rps()
4887 I915_WRITE(GEN6_RC_VIDEO_FREQ, in gen8_enable_rps()
4890 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ in gen8_enable_rps()
4893 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, in gen8_enable_rps()
4897 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ in gen8_enable_rps()
4898 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ in gen8_enable_rps()
4899 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ in gen8_enable_rps()
4900 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ in gen8_enable_rps()
4902 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); in gen8_enable_rps()
4905 I915_WRITE(GEN6_RP_CONTROL, in gen8_enable_rps()
4938 I915_WRITE(GEN6_RC_STATE, 0); in gen6_enable_rps()
4943 I915_WRITE(GTFIFODBG, gtfifodbg); in gen6_enable_rps()
4952 I915_WRITE(GEN6_RC_CONTROL, 0); in gen6_enable_rps()
4954 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); in gen6_enable_rps()
4955 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); in gen6_enable_rps()
4956 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); in gen6_enable_rps()
4957 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); in gen6_enable_rps()
4958 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); in gen6_enable_rps()
4961 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); in gen6_enable_rps()
4963 I915_WRITE(GEN6_RC_SLEEP, 0); in gen6_enable_rps()
4964 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); in gen6_enable_rps()
4966 I915_WRITE(GEN6_RC6_THRESHOLD, 125000); in gen6_enable_rps()
4968 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); in gen6_enable_rps()
4969 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); in gen6_enable_rps()
4970 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ in gen6_enable_rps()
4988 I915_WRITE(GEN6_RC_CONTROL, in gen6_enable_rps()
4994 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); in gen6_enable_rps()
4995 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); in gen6_enable_rps()
5251 I915_WRITE(VLV_PCBR, pctx_paddr); in cherryview_setup_pctx()
5297 I915_WRITE(VLV_PCBR, pctx_paddr); in valleyview_setup_pctx()
5453 I915_WRITE(GTFIFODBG, gtfifodbg); in cherryview_enable_rps()
5463 I915_WRITE(GEN6_RC_CONTROL, 0); in cherryview_enable_rps()
5466 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); in cherryview_enable_rps()
5467 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in cherryview_enable_rps()
5468 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in cherryview_enable_rps()
5471 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); in cherryview_enable_rps()
5472 I915_WRITE(GEN6_RC_SLEEP, 0); in cherryview_enable_rps()
5475 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); in cherryview_enable_rps()
5478 I915_WRITE(VLV_COUNTER_CONTROL, in cherryview_enable_rps()
5491 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); in cherryview_enable_rps()
5494 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); in cherryview_enable_rps()
5495 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); in cherryview_enable_rps()
5496 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); in cherryview_enable_rps()
5497 I915_WRITE(GEN6_RP_UP_EI, 66000); in cherryview_enable_rps()
5498 I915_WRITE(GEN6_RP_DOWN_EI, 350000); in cherryview_enable_rps()
5500 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); in cherryview_enable_rps()
5503 I915_WRITE(GEN6_RP_CONTROL, in cherryview_enable_rps()
5552 I915_WRITE(GTFIFODBG, gtfifodbg); in valleyview_enable_rps()
5559 I915_WRITE(GEN6_RC_CONTROL, 0); in valleyview_enable_rps()
5561 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); in valleyview_enable_rps()
5562 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); in valleyview_enable_rps()
5563 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); in valleyview_enable_rps()
5564 I915_WRITE(GEN6_RP_UP_EI, 66000); in valleyview_enable_rps()
5565 I915_WRITE(GEN6_RP_DOWN_EI, 350000); in valleyview_enable_rps()
5567 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); in valleyview_enable_rps()
5569 I915_WRITE(GEN6_RP_CONTROL, in valleyview_enable_rps()
5577 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); in valleyview_enable_rps()
5578 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); in valleyview_enable_rps()
5579 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); in valleyview_enable_rps()
5582 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); in valleyview_enable_rps()
5584 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); in valleyview_enable_rps()
5587 I915_WRITE(VLV_COUNTER_CONTROL, in valleyview_enable_rps()
5598 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); in valleyview_enable_rps()
6053 I915_WRITE(ECR, 0); in intel_init_emon()
6057 I915_WRITE(SDEW, 0x15040d00); in intel_init_emon()
6058 I915_WRITE(CSIEW0, 0x007f0000); in intel_init_emon()
6059 I915_WRITE(CSIEW1, 0x1e220004); in intel_init_emon()
6060 I915_WRITE(CSIEW2, 0x04000004); in intel_init_emon()
6063 I915_WRITE(PEW(i), 0); in intel_init_emon()
6065 I915_WRITE(DEW(i), 0); in intel_init_emon()
6090 I915_WRITE(PXW(i), val); in intel_init_emon()
6094 I915_WRITE(OGW0, 0); in intel_init_emon()
6095 I915_WRITE(OGW1, 0); in intel_init_emon()
6096 I915_WRITE(EG0, 0x00007f00); in intel_init_emon()
6097 I915_WRITE(EG1, 0x0000000e); in intel_init_emon()
6098 I915_WRITE(EG2, 0x000e0000); in intel_init_emon()
6099 I915_WRITE(EG3, 0x68000300); in intel_init_emon()
6100 I915_WRITE(EG4, 0x42000000); in intel_init_emon()
6101 I915_WRITE(EG5, 0x00140031); in intel_init_emon()
6102 I915_WRITE(EG6, 0); in intel_init_emon()
6103 I915_WRITE(EG7, 0); in intel_init_emon()
6106 I915_WRITE(PXWL(i), 0); in intel_init_emon()
6109 I915_WRITE(ECR, 0x80000019); in intel_init_emon()
6283 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); in ibx_init_clock_gating()
6292 I915_WRITE(DSPCNTR(pipe), in g4x_disable_trickle_feed()
6296 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); in g4x_disable_trickle_feed()
6305 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); in ilk_init_lp_watermarks()
6306 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); in ilk_init_lp_watermarks()
6307 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); in ilk_init_lp_watermarks()
6328 I915_WRITE(PCH_3DCGDIS0, in ironlake_init_clock_gating()
6331 I915_WRITE(PCH_3DCGDIS1, in ironlake_init_clock_gating()
6341 I915_WRITE(ILK_DISPLAY_CHICKEN2, in ironlake_init_clock_gating()
6345 I915_WRITE(DISP_ARB_CTL, in ironlake_init_clock_gating()
6360 I915_WRITE(ILK_DISPLAY_CHICKEN1, in ironlake_init_clock_gating()
6363 I915_WRITE(ILK_DISPLAY_CHICKEN2, in ironlake_init_clock_gating()
6368 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); in ironlake_init_clock_gating()
6370 I915_WRITE(ILK_DISPLAY_CHICKEN2, in ironlake_init_clock_gating()
6373 I915_WRITE(_3D_CHICKEN2, in ironlake_init_clock_gating()
6378 I915_WRITE(CACHE_MODE_0, in ironlake_init_clock_gating()
6382 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in ironlake_init_clock_gating()
6400 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | in cpt_init_clock_gating()
6403 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | in cpt_init_clock_gating()
6417 I915_WRITE(TRANS_CHICKEN2(pipe), val); in cpt_init_clock_gating()
6421 I915_WRITE(TRANS_CHICKEN1(pipe), in cpt_init_clock_gating()
6442 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); in gen6_init_clock_gating()
6444 I915_WRITE(ILK_DISPLAY_CHICKEN2, in gen6_init_clock_gating()
6449 I915_WRITE(_3D_CHICKEN, in gen6_init_clock_gating()
6453 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in gen6_init_clock_gating()
6463 I915_WRITE(GEN6_GT_MODE, in gen6_init_clock_gating()
6468 I915_WRITE(CACHE_MODE_0, in gen6_init_clock_gating()
6471 I915_WRITE(GEN6_UCGCTL1, in gen6_init_clock_gating()
6489 I915_WRITE(GEN6_UCGCTL2, in gen6_init_clock_gating()
6494 I915_WRITE(_3D_CHICKEN3, in gen6_init_clock_gating()
6502 I915_WRITE(_3D_CHICKEN3, in gen6_init_clock_gating()
6516 I915_WRITE(ILK_DISPLAY_CHICKEN1, in gen6_init_clock_gating()
6519 I915_WRITE(ILK_DISPLAY_CHICKEN2, in gen6_init_clock_gating()
6522 I915_WRITE(ILK_DSPCLK_GATE_D, in gen6_init_clock_gating()
6549 I915_WRITE(GEN7_FF_THREAD_MODE, reg); in gen7_setup_fixed_func_scheduler()
6561 I915_WRITE(SOUTH_DSPCLK_GATE_D, in lpt_init_clock_gating()
6566 I915_WRITE(TRANS_CHICKEN1(PIPE_A), in lpt_init_clock_gating()
6579 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); in lpt_suspend_hw()
6592 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); in broadwell_init_clock_gating()
6595 I915_WRITE(CHICKEN_PAR1_1, in broadwell_init_clock_gating()
6600 I915_WRITE(CHICKEN_PIPESL_1(pipe), in broadwell_init_clock_gating()
6607 I915_WRITE(GEN7_FF_THREAD_MODE, in broadwell_init_clock_gating()
6611 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, in broadwell_init_clock_gating()
6615 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in broadwell_init_clock_gating()
6623 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in broadwell_init_clock_gating()
6624 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); in broadwell_init_clock_gating()
6631 I915_WRITE(GEN7_MISCCPCTL, misccpctl); in broadwell_init_clock_gating()
6638 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); in broadwell_init_clock_gating()
6650 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); in haswell_init_clock_gating()
6651 I915_WRITE(HSW_ROW_CHICKEN3, in haswell_init_clock_gating()
6655 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in haswell_init_clock_gating()
6660 I915_WRITE(GEN7_FF_THREAD_MODE, in haswell_init_clock_gating()
6664 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in haswell_init_clock_gating()
6667 I915_WRITE(CACHE_MODE_0_GEN7, in haswell_init_clock_gating()
6671 I915_WRITE(CACHE_MODE_1, in haswell_init_clock_gating()
6682 I915_WRITE(GEN7_GT_MODE, in haswell_init_clock_gating()
6686 I915_WRITE(HALF_SLICE_CHICKEN3, in haswell_init_clock_gating()
6690 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); in haswell_init_clock_gating()
6693 I915_WRITE(CHICKEN_PAR1_1, in haswell_init_clock_gating()
6706 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); in ivybridge_init_clock_gating()
6709 I915_WRITE(_3D_CHICKEN3, in ivybridge_init_clock_gating()
6713 I915_WRITE(IVB_CHICKEN3, in ivybridge_init_clock_gating()
6719 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, in ivybridge_init_clock_gating()
6723 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in ivybridge_init_clock_gating()
6726 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, in ivybridge_init_clock_gating()
6730 I915_WRITE(GEN7_L3CNTLREG1, in ivybridge_init_clock_gating()
6732 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, in ivybridge_init_clock_gating()
6735 I915_WRITE(GEN7_ROW_CHICKEN2, in ivybridge_init_clock_gating()
6739 I915_WRITE(GEN7_ROW_CHICKEN2, in ivybridge_init_clock_gating()
6741 I915_WRITE(GEN7_ROW_CHICKEN2_GT2, in ivybridge_init_clock_gating()
6746 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & in ivybridge_init_clock_gating()
6753 I915_WRITE(GEN6_UCGCTL2, in ivybridge_init_clock_gating()
6757 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in ivybridge_init_clock_gating()
6767 I915_WRITE(CACHE_MODE_0_GEN7, in ivybridge_init_clock_gating()
6772 I915_WRITE(CACHE_MODE_1, in ivybridge_init_clock_gating()
6783 I915_WRITE(GEN7_GT_MODE, in ivybridge_init_clock_gating()
6789 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); in ivybridge_init_clock_gating()
6799 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); in vlv_init_display_clock_gating()
6804 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); in vlv_init_display_clock_gating()
6805 I915_WRITE(CBR1_VLV, 0); in vlv_init_display_clock_gating()
6815 I915_WRITE(_3D_CHICKEN3, in valleyview_init_clock_gating()
6819 I915_WRITE(IVB_CHICKEN3, in valleyview_init_clock_gating()
6825 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, in valleyview_init_clock_gating()
6830 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in valleyview_init_clock_gating()
6833 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & in valleyview_init_clock_gating()
6837 I915_WRITE(GEN7_ROW_CHICKEN2, in valleyview_init_clock_gating()
6841 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in valleyview_init_clock_gating()
6851 I915_WRITE(GEN6_UCGCTL2, in valleyview_init_clock_gating()
6857 I915_WRITE(GEN7_UCGCTL4, in valleyview_init_clock_gating()
6864 I915_WRITE(CACHE_MODE_1, in valleyview_init_clock_gating()
6875 I915_WRITE(GEN7_GT_MODE, in valleyview_init_clock_gating()
6882 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); in valleyview_init_clock_gating()
6889 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); in valleyview_init_clock_gating()
6900 I915_WRITE(GEN7_FF_THREAD_MODE, in cherryview_init_clock_gating()
6905 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, in cherryview_init_clock_gating()
6909 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | in cherryview_init_clock_gating()
6913 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in cherryview_init_clock_gating()
6920 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); in cherryview_init_clock_gating()
6928 I915_WRITE(RENCLK_GATE_D1, 0); in g4x_init_clock_gating()
6929 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | in g4x_init_clock_gating()
6932 I915_WRITE(RAMCLK_GATE_D, 0); in g4x_init_clock_gating()
6938 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); in g4x_init_clock_gating()
6941 I915_WRITE(CACHE_MODE_0, in g4x_init_clock_gating()
6945 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in g4x_init_clock_gating()
6954 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); in crestline_init_clock_gating()
6955 I915_WRITE(RENCLK_GATE_D2, 0); in crestline_init_clock_gating()
6956 I915_WRITE(DSPCLK_GATE_D, 0); in crestline_init_clock_gating()
6957 I915_WRITE(RAMCLK_GATE_D, 0); in crestline_init_clock_gating()
6959 I915_WRITE(MI_ARB_STATE, in crestline_init_clock_gating()
6963 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in crestline_init_clock_gating()
6970 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | in broadwater_init_clock_gating()
6975 I915_WRITE(RENCLK_GATE_D2, 0); in broadwater_init_clock_gating()
6976 I915_WRITE(MI_ARB_STATE, in broadwater_init_clock_gating()
6980 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in broadwater_init_clock_gating()
6990 I915_WRITE(D_STATE, dstate); in gen3_init_clock_gating()
6993 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); in gen3_init_clock_gating()
6996 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); in gen3_init_clock_gating()
6999 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); in gen3_init_clock_gating()
7002 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); in gen3_init_clock_gating()
7004 I915_WRITE(MI_ARB_STATE, in gen3_init_clock_gating()
7012 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); in i85x_init_clock_gating()
7015 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | in i85x_init_clock_gating()
7018 I915_WRITE(MEM_MODE, in i85x_init_clock_gating()
7026 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); in i830_init_clock_gating()
7028 I915_WRITE(MEM_MODE, in i830_init_clock_gating()
7161 I915_WRITE(GEN6_PCODE_DATA, *val); in sandybridge_pcode_read()
7162 I915_WRITE(GEN6_PCODE_DATA1, 0); in sandybridge_pcode_read()
7163 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); in sandybridge_pcode_read()
7172 I915_WRITE(GEN6_PCODE_DATA, 0); in sandybridge_pcode_read()
7186 I915_WRITE(GEN6_PCODE_DATA, val); in sandybridge_pcode_write()
7187 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); in sandybridge_pcode_write()
7195 I915_WRITE(GEN6_PCODE_DATA, 0); in sandybridge_pcode_write()