600 	struct drm_crtc *crtc, *enabled = NULL;  in single_enabled_crtc()  local
602 	for_each_crtc(dev, crtc) {  in single_enabled_crtc()
603 		if (intel_crtc_active(crtc)) {  in single_enabled_crtc()
606 			enabled = crtc;  in single_enabled_crtc()
617 	struct drm_crtc *crtc;  in pineview_update_wm()  local
630 	crtc = single_enabled_crtc(dev);  in pineview_update_wm()
631 	if (crtc) {  in pineview_update_wm()
632 		const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;  in pineview_update_wm()
633 		int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;  in pineview_update_wm()
689 	struct drm_crtc *crtc;  in g4x_compute_wm0()  local
695 	crtc = intel_get_crtc_for_plane(dev, plane);  in g4x_compute_wm0()
696 	if (!intel_crtc_active(crtc)) {  in g4x_compute_wm0()
702 	adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;  in g4x_compute_wm0()
705 	hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;  in g4x_compute_wm0()
706 	pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;  in g4x_compute_wm0()
721 	entries = line_count * crtc->cursor->state->crtc_w * pixel_size;  in g4x_compute_wm0()
775 	struct drm_crtc *crtc;  in g4x_compute_srwm()  local
788 	crtc = intel_get_crtc_for_plane(dev, plane);  in g4x_compute_srwm()
789 	adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;  in g4x_compute_srwm()
792 	hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;  in g4x_compute_srwm()
793 	pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;  in g4x_compute_srwm()
807 	entries = line_count * pixel_size * crtc->cursor->state->crtc_w;  in g4x_compute_srwm()
819 static void vlv_write_wm_values(struct intel_crtc *crtc,  in vlv_write_wm_values()  argument
822 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in vlv_write_wm_values()
823 	enum pipe pipe = crtc->pipe;  in vlv_write_wm_values()
929 				     struct intel_crtc *crtc,  in vlv_compute_wm_level()  argument
943 	clock = crtc->config->base.adjusted_mode.crtc_clock;  in vlv_compute_wm_level()
944 	htotal = crtc->config->base.adjusted_mode.crtc_htotal;  in vlv_compute_wm_level()
945 	width = crtc->config->pipe_src_w;  in vlv_compute_wm_level()
965 static void vlv_compute_fifo(struct intel_crtc *crtc)  in vlv_compute_fifo()  argument
967 	struct drm_device *dev = crtc->base.dev;  in vlv_compute_fifo()
968 	struct vlv_wm_state *wm_state = &crtc->wm_state;  in vlv_compute_fifo()
974 	for_each_intel_plane_on_crtc(dev, crtc, plane) {  in vlv_compute_fifo()
987 	for_each_intel_plane_on_crtc(dev, crtc, plane) {  in vlv_compute_fifo()
1010 	for_each_intel_plane_on_crtc(dev, crtc, plane) {  in vlv_compute_fifo()
1032 static void vlv_invert_wms(struct intel_crtc *crtc)  in vlv_invert_wms()  argument
1034 	struct vlv_wm_state *wm_state = &crtc->wm_state;  in vlv_invert_wms()
1038 		struct drm_device *dev = crtc->base.dev;  in vlv_invert_wms()
1045 		for_each_intel_plane_on_crtc(dev, crtc, plane) {  in vlv_invert_wms()
1066 static void vlv_compute_wm(struct intel_crtc *crtc)  in vlv_compute_wm()  argument
1068 	struct drm_device *dev = crtc->base.dev;  in vlv_compute_wm()
1069 	struct vlv_wm_state *wm_state = &crtc->wm_state;  in vlv_compute_wm()
1076 	wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;  in vlv_compute_wm()
1081 	vlv_compute_fifo(crtc);  in vlv_compute_wm()
1093 	for_each_intel_plane_on_crtc(dev, crtc, plane) {  in vlv_compute_wm()
1102 			int wm = vlv_compute_wm_level(plane, crtc, state, level);  in vlv_compute_wm()
1162 	vlv_invert_wms(crtc);  in vlv_compute_wm()
1168 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)  in vlv_pipe_set_fifo_size()  argument
1170 	struct drm_device *dev = crtc->base.dev;  in vlv_pipe_set_fifo_size()
1175 	for_each_intel_plane_on_crtc(dev, crtc, plane) {  in vlv_pipe_set_fifo_size()
1192 		      pipe_name(crtc->pipe), sprite0_start,  in vlv_pipe_set_fifo_size()
1195 	switch (crtc->pipe) {  in vlv_pipe_set_fifo_size()
1258 	struct intel_crtc *crtc;  in vlv_merge_wm()  local
1264 	for_each_intel_crtc(dev, crtc) {  in vlv_merge_wm()
1265 		const struct vlv_wm_state *wm_state = &crtc->wm_state;  in vlv_merge_wm()
1267 		if (!crtc->active)  in vlv_merge_wm()
1283 	for_each_intel_crtc(dev, crtc) {  in vlv_merge_wm()
1284 		struct vlv_wm_state *wm_state = &crtc->wm_state;  in vlv_merge_wm()
1285 		enum pipe pipe = crtc->pipe;  in vlv_merge_wm()
1287 		if (!crtc->active)  in vlv_merge_wm()
1301 static void vlv_update_wm(struct drm_crtc *crtc)  in vlv_update_wm()  argument
1303 	struct drm_device *dev = crtc->dev;  in vlv_update_wm()
1305 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in vlv_update_wm()
1356 static void g4x_update_wm(struct drm_crtc *crtc)  in g4x_update_wm()  argument
1358 	struct drm_device *dev = crtc->dev;  in g4x_update_wm()
1418 	struct drm_crtc *crtc;  in i965_update_wm()  local
1424 	crtc = single_enabled_crtc(dev);  in i965_update_wm()
1425 	if (crtc) {  in i965_update_wm()
1428 		const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;  in i965_update_wm()
1431 		int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;  in i965_update_wm()
1432 		int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;  in i965_update_wm()
1450 			pixel_size * crtc->cursor->state->crtc_w;  in i965_update_wm()
1498 	struct drm_crtc *crtc, *enabled = NULL;  in i9xx_update_wm()  local
1508 	crtc = intel_get_crtc_for_plane(dev, 0);  in i9xx_update_wm()
1509 	if (intel_crtc_active(crtc)) {  in i9xx_update_wm()
1511 		int cpp = crtc->primary->state->fb->bits_per_pixel / 8;  in i9xx_update_wm()
1515 		adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;  in i9xx_update_wm()
1519 		enabled = crtc;  in i9xx_update_wm()
1530 	crtc = intel_get_crtc_for_plane(dev, 1);  in i9xx_update_wm()
1531 	if (intel_crtc_active(crtc)) {  in i9xx_update_wm()
1533 		int cpp = crtc->primary->state->fb->bits_per_pixel / 8;  in i9xx_update_wm()
1537 		adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;  in i9xx_update_wm()
1542 			enabled = crtc;  in i9xx_update_wm()
1622 	struct drm_crtc *crtc;  in i845_update_wm()  local
1627 	crtc = single_enabled_crtc(dev);  in i845_update_wm()
1628 	if (crtc == NULL)  in i845_update_wm()
1631 	adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;  in i845_update_wm()
2023 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)  in hsw_compute_linetime_wm()  argument
2026 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in hsw_compute_linetime_wm()
2299 	struct drm_crtc *crtc = cstate->base.crtc;  in intel_compute_pipe_wm()  local
2300 	struct drm_device *dev = crtc->dev;  in intel_compute_pipe_wm()
2302 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in intel_compute_pipe_wm()
2339 		pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);  in intel_compute_pipe_wm()
2765 	struct drm_crtc *crtc;  in skl_ddb_get_pipe_allocation_limits()  local
2783 	for_each_crtc(dev, crtc) {  in skl_ddb_get_pipe_allocation_limits()
2784 		if (!to_intel_crtc(crtc)->active)  in skl_ddb_get_pipe_allocation_limits()
2787 		if (crtc == for_crtc)  in skl_ddb_get_pipe_allocation_limits()
2884 skl_allocate_pipe_ddb(struct drm_crtc *crtc,  in skl_allocate_pipe_ddb()  argument
2889 	struct drm_device *dev = crtc->dev;  in skl_allocate_pipe_ddb()
2891 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_allocate_pipe_ddb()
2900 	skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);  in skl_allocate_pipe_ddb()
3060 	struct drm_crtc *crtc;  in skl_compute_wm_global_parameters()  local
3063 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)  in skl_compute_wm_global_parameters()
3064 		config->num_pipes_active += to_intel_crtc(crtc)->active;  in skl_compute_wm_global_parameters()
3075 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,  in skl_compute_wm_pipe_parameters()  argument
3078 	struct drm_device *dev = crtc->dev;  in skl_compute_wm_pipe_parameters()
3079 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_compute_wm_pipe_parameters()
3090 		fb = crtc->primary->state->fb;  in skl_compute_wm_pipe_parameters()
3108 		p->plane[0].rotation = crtc->primary->state->rotation;  in skl_compute_wm_pipe_parameters()
3110 		fb = crtc->cursor->state->fb;  in skl_compute_wm_pipe_parameters()
3115 			p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w;  in skl_compute_wm_pipe_parameters()
3116 			p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h;  in skl_compute_wm_pipe_parameters()
3244 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)  in skl_compute_linetime_wm()  argument
3246 	if (!to_intel_crtc(crtc)->active)  in skl_compute_linetime_wm()
3255 static void skl_compute_transition_wm(struct drm_crtc *crtc,  in skl_compute_transition_wm()  argument
3259 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_compute_transition_wm()
3271 static void skl_compute_pipe_wm(struct drm_crtc *crtc,  in skl_compute_pipe_wm()  argument
3276 	struct drm_device *dev = crtc->dev;  in skl_compute_pipe_wm()
3278 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_compute_pipe_wm()
3286 	pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);  in skl_compute_pipe_wm()
3288 	skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);  in skl_compute_pipe_wm()
3362 	struct intel_crtc *crtc;  in skl_write_wm_values()  local
3364 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {  in skl_write_wm_values()
3366 		enum pipe pipe = crtc->pipe;  in skl_write_wm_values()
3374 			for (i = 0; i < intel_num_planes(crtc); i++)  in skl_write_wm_values()
3380 		for (i = 0; i < intel_num_planes(crtc); i++)  in skl_write_wm_values()
3386 		for (i = 0; i < intel_num_planes(crtc); i++) {  in skl_write_wm_values()
3459 	struct intel_crtc *crtc;  in skl_flush_wm_values()  local
3472 	for_each_intel_crtc(dev, crtc) {  in skl_flush_wm_values()
3473 		if (!crtc->active)  in skl_flush_wm_values()
3476 		pipe = crtc->pipe;  in skl_flush_wm_values()
3495 	for_each_intel_crtc(dev, crtc) {  in skl_flush_wm_values()
3496 		if (!crtc->active)  in skl_flush_wm_values()
3499 		pipe = crtc->pipe;  in skl_flush_wm_values()
3518 	for_each_intel_crtc(dev, crtc) {  in skl_flush_wm_values()
3519 		if (!crtc->active)  in skl_flush_wm_values()
3522 		pipe = crtc->pipe;  in skl_flush_wm_values()
3535 static bool skl_update_pipe_wm(struct drm_crtc *crtc,  in skl_update_pipe_wm()  argument
3541 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_update_pipe_wm()
3543 	skl_compute_wm_pipe_parameters(crtc, params);  in skl_update_pipe_wm()
3544 	skl_allocate_pipe_ddb(crtc, config, params, ddb);  in skl_update_pipe_wm()
3545 	skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);  in skl_update_pipe_wm()
3556 				     struct drm_crtc *crtc,  in skl_update_other_pipe_wm()  argument
3561 	struct intel_crtc *this_crtc = to_intel_crtc(crtc);  in skl_update_other_pipe_wm()
3624 static void skl_update_wm(struct drm_crtc *crtc)  in skl_update_wm()  argument
3626 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_update_wm()
3627 	struct drm_device *dev = crtc->dev;  in skl_update_wm()
3642 	if (!skl_update_pipe_wm(crtc, &params, &config,  in skl_update_wm()
3649 	skl_update_other_pipe_wm(dev, crtc, &config, results);  in skl_update_wm()
3658 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,  in skl_update_sprite_wm()  argument
3687 	skl_update_wm(crtc);  in skl_update_sprite_wm()
3690 static void ilk_update_wm(struct drm_crtc *crtc)  in ilk_update_wm()  argument
3692 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in ilk_update_wm()
3693 	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);  in ilk_update_wm()
3694 	struct drm_device *dev = crtc->dev;  in ilk_update_wm()
3738 		     struct drm_crtc *crtc,  in ilk_update_sprite_wm()  argument
3755 	ilk_update_wm(crtc);  in ilk_update_sprite_wm()
3802 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)  in skl_pipe_wm_get_hw_state()  argument
3804 	struct drm_device *dev = crtc->dev;  in skl_pipe_wm_get_hw_state()
3807 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_pipe_wm_get_hw_state()
3858 	struct drm_crtc *crtc;  in skl_wm_get_hw_state()  local
3861 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)  in skl_wm_get_hw_state()
3862 		skl_pipe_wm_get_hw_state(crtc);  in skl_wm_get_hw_state()
3865 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)  in ilk_pipe_wm_get_hw_state()  argument
3867 	struct drm_device *dev = crtc->dev;  in ilk_pipe_wm_get_hw_state()
3870 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in ilk_pipe_wm_get_hw_state()
4071 	struct drm_crtc *crtc;  in ilk_wm_get_hw_state()  local
4073 	for_each_crtc(dev, crtc)  in ilk_wm_get_hw_state()
4074 		ilk_pipe_wm_get_hw_state(crtc);  in ilk_wm_get_hw_state()
4129 void intel_update_watermarks(struct drm_crtc *crtc)  in intel_update_watermarks()  argument
4131 	struct drm_i915_private *dev_priv = crtc->dev->dev_private;  in intel_update_watermarks()
4134 		dev_priv->display.update_wm(crtc);  in intel_update_watermarks()
4138 				    struct drm_crtc *crtc,  in intel_update_sprite_watermarks()  argument
4147 		dev_priv->display.update_sprite_wm(plane, crtc,  in intel_update_sprite_watermarks()