Lines Matching refs:plane
278 #define FW_WM(value, plane) \ argument
279 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
337 enum pipe pipe, int plane) in vlv_get_fifo_size() argument
366 switch (plane) { in vlv_get_fifo_size()
381 pipe_name(pipe), plane == 0 ? "primary" : "sprite", in vlv_get_fifo_size()
382 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1), in vlv_get_fifo_size()
388 static int i9xx_get_fifo_size(struct drm_device *dev, int plane) in i9xx_get_fifo_size() argument
395 if (plane) in i9xx_get_fifo_size()
399 plane ? "B" : "A", size); in i9xx_get_fifo_size()
404 static int i830_get_fifo_size(struct drm_device *dev, int plane) in i830_get_fifo_size() argument
411 if (plane) in i830_get_fifo_size()
416 plane ? "B" : "A", size); in i830_get_fifo_size()
421 static int i845_get_fifo_size(struct drm_device *dev, int plane) in i845_get_fifo_size() argument
431 plane ? "B" : "A", in i845_get_fifo_size()
681 int plane, in g4x_compute_wm0() argument
695 crtc = intel_get_crtc_for_plane(dev, plane); in g4x_compute_wm0()
769 int plane, in g4x_compute_srwm() argument
788 crtc = intel_get_crtc_for_plane(dev, plane); in g4x_compute_srwm()
816 #define FW_WM_VLV(value, plane) \ argument
817 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
832 FW_WM(wm->sr.plane, SR) | in vlv_write_wm_values()
854 FW_WM(wm->sr.plane >> 9, SR_HI) | in vlv_write_wm_values()
869 FW_WM(wm->sr.plane >> 9, SR_HI) | in vlv_write_wm_values()
928 static uint16_t vlv_compute_wm_level(struct intel_plane *plane, in vlv_compute_wm_level() argument
933 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in vlv_compute_wm_level()
949 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { in vlv_compute_wm_level()
969 struct intel_plane *plane; in vlv_compute_fifo() local
974 for_each_intel_plane_on_crtc(dev, crtc, plane) { in vlv_compute_fifo()
976 to_intel_plane_state(plane->base.state); in vlv_compute_fifo()
978 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) in vlv_compute_fifo()
987 for_each_intel_plane_on_crtc(dev, crtc, plane) { in vlv_compute_fifo()
989 to_intel_plane_state(plane->base.state); in vlv_compute_fifo()
992 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { in vlv_compute_fifo()
993 plane->wm.fifo_size = 63; in vlv_compute_fifo()
998 plane->wm.fifo_size = 0; in vlv_compute_fifo()
1003 plane->wm.fifo_size = fifo_size * rate / total_rate; in vlv_compute_fifo()
1004 fifo_left -= plane->wm.fifo_size; in vlv_compute_fifo()
1010 for_each_intel_plane_on_crtc(dev, crtc, plane) { in vlv_compute_fifo()
1016 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) in vlv_compute_fifo()
1020 if (plane->wm.fifo_size == 0 && in vlv_compute_fifo()
1025 plane->wm.fifo_size += plane_extra; in vlv_compute_fifo()
1040 struct intel_plane *plane; in vlv_invert_wms() local
1042 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane; in vlv_invert_wms()
1045 for_each_intel_plane_on_crtc(dev, crtc, plane) { in vlv_invert_wms()
1046 switch (plane->base.type) { in vlv_invert_wms()
1049 wm_state->wm[level].cursor = plane->wm.fifo_size - in vlv_invert_wms()
1053 wm_state->wm[level].primary = plane->wm.fifo_size - in vlv_invert_wms()
1057 sprite = plane->plane; in vlv_invert_wms()
1058 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size - in vlv_invert_wms()
1070 struct intel_plane *plane; in vlv_compute_wm() local
1088 wm_state->sr[level].plane = sr_fifo_size; in vlv_compute_wm()
1093 for_each_intel_plane_on_crtc(dev, crtc, plane) { in vlv_compute_wm()
1095 to_intel_plane_state(plane->base.state); in vlv_compute_wm()
1102 int wm = vlv_compute_wm_level(plane, crtc, state, level); in vlv_compute_wm()
1103 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511; in vlv_compute_wm()
1109 if (wm > plane->wm.fifo_size) in vlv_compute_wm()
1112 switch (plane->base.type) { in vlv_compute_wm()
1121 sprite = plane->plane; in vlv_compute_wm()
1133 switch (plane->base.type) { in vlv_compute_wm()
1142 wm_state->sr[level].plane = in vlv_compute_wm()
1143 min(wm_state->sr[level].plane, in vlv_compute_wm()
1147 sprite = plane->plane; in vlv_compute_wm()
1149 wm_state->sr[level].plane = in vlv_compute_wm()
1150 min(wm_state->sr[level].plane, in vlv_compute_wm()
1165 #define VLV_FIFO(plane, value) \ argument
1166 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1172 struct intel_plane *plane; in vlv_pipe_set_fifo_size() local
1175 for_each_intel_plane_on_crtc(dev, crtc, plane) { in vlv_pipe_set_fifo_size()
1176 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { in vlv_pipe_set_fifo_size()
1177 WARN_ON(plane->wm.fifo_size != 63); in vlv_pipe_set_fifo_size()
1181 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) in vlv_pipe_set_fifo_size()
1182 sprite0_start = plane->wm.fifo_size; in vlv_pipe_set_fifo_size()
1183 else if (plane->plane == 0) in vlv_pipe_set_fifo_size()
1184 sprite1_start = sprite0_start + plane->wm.fifo_size; in vlv_pipe_set_fifo_size()
1186 fifo_size = sprite1_start + plane->wm.fifo_size; in vlv_pipe_set_fifo_size()
1338 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr); in vlv_update_wm()
1715 struct intel_plane_wm_parameters plane[I915_MAX_PLANES]; member
2818 int plane; in skl_ddb_get_hw_state() local
2827 for_each_plane(dev_priv, pipe, plane) { in skl_ddb_get_hw_state()
2828 val = I915_READ(PLANE_BUF_CFG(pipe, plane)); in skl_ddb_get_hw_state()
2829 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], in skl_ddb_get_hw_state()
2834 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR], in skl_ddb_get_hw_state()
2865 int plane; in skl_get_total_relative_data_rate() local
2867 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { in skl_get_total_relative_data_rate()
2870 p = ¶ms->plane[plane]; in skl_get_total_relative_data_rate()
2898 int plane; in skl_allocate_pipe_ddb() local
2903 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); in skl_allocate_pipe_ddb()
2904 memset(&ddb->plane[pipe][PLANE_CURSOR], 0, in skl_allocate_pipe_ddb()
2905 sizeof(ddb->plane[pipe][PLANE_CURSOR])); in skl_allocate_pipe_ddb()
2910 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks; in skl_allocate_pipe_ddb()
2911 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end; in skl_allocate_pipe_ddb()
2917 for_each_plane(dev_priv, pipe, plane) { in skl_allocate_pipe_ddb()
2920 p = ¶ms->plane[plane]; in skl_allocate_pipe_ddb()
2924 minimum[plane] = 8; in skl_allocate_pipe_ddb()
2925 alloc_size -= minimum[plane]; in skl_allocate_pipe_ddb()
2926 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0; in skl_allocate_pipe_ddb()
2927 alloc_size -= y_minimum[plane]; in skl_allocate_pipe_ddb()
2939 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { in skl_allocate_pipe_ddb()
2944 p = ¶ms->plane[plane]; in skl_allocate_pipe_ddb()
2955 plane_blocks = minimum[plane]; in skl_allocate_pipe_ddb()
2959 ddb->plane[pipe][plane].start = start; in skl_allocate_pipe_ddb()
2960 ddb->plane[pipe][plane].end = start + plane_blocks; in skl_allocate_pipe_ddb()
2969 y_plane_blocks = y_minimum[plane]; in skl_allocate_pipe_ddb()
2973 ddb->y_plane[pipe][plane].start = start; in skl_allocate_pipe_ddb()
2974 ddb->y_plane[pipe][plane].end = start + y_plane_blocks; in skl_allocate_pipe_ddb()
3046 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], in skl_ddb_allocation_changed()
3047 sizeof(new_ddb->plane[pipe]))) in skl_ddb_allocation_changed()
3050 if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR], in skl_ddb_allocation_changed()
3051 sizeof(new_ddb->plane[pipe][PLANE_CURSOR]))) in skl_ddb_allocation_changed()
3061 struct drm_plane *plane; in skl_compute_wm_global_parameters() local
3067 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { in skl_compute_wm_global_parameters()
3068 struct intel_plane *intel_plane = to_intel_plane(plane); in skl_compute_wm_global_parameters()
3081 struct drm_plane *plane; in skl_compute_wm_pipe_parameters() local
3093 p->plane[0].enabled = true; in skl_compute_wm_pipe_parameters()
3094 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? in skl_compute_wm_pipe_parameters()
3097 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? in skl_compute_wm_pipe_parameters()
3099 p->plane[0].tiling = fb->modifier[0]; in skl_compute_wm_pipe_parameters()
3101 p->plane[0].enabled = false; in skl_compute_wm_pipe_parameters()
3102 p->plane[0].bytes_per_pixel = 0; in skl_compute_wm_pipe_parameters()
3103 p->plane[0].y_bytes_per_pixel = 0; in skl_compute_wm_pipe_parameters()
3104 p->plane[0].tiling = DRM_FORMAT_MOD_NONE; in skl_compute_wm_pipe_parameters()
3106 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; in skl_compute_wm_pipe_parameters()
3107 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h; in skl_compute_wm_pipe_parameters()
3108 p->plane[0].rotation = crtc->primary->state->rotation; in skl_compute_wm_pipe_parameters()
3111 p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0; in skl_compute_wm_pipe_parameters()
3113 p->plane[PLANE_CURSOR].enabled = true; in skl_compute_wm_pipe_parameters()
3114 p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8; in skl_compute_wm_pipe_parameters()
3115 p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w; in skl_compute_wm_pipe_parameters()
3116 p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h; in skl_compute_wm_pipe_parameters()
3118 p->plane[PLANE_CURSOR].enabled = false; in skl_compute_wm_pipe_parameters()
3119 p->plane[PLANE_CURSOR].bytes_per_pixel = 0; in skl_compute_wm_pipe_parameters()
3120 p->plane[PLANE_CURSOR].horiz_pixels = 64; in skl_compute_wm_pipe_parameters()
3121 p->plane[PLANE_CURSOR].vert_pixels = 64; in skl_compute_wm_pipe_parameters()
3125 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { in skl_compute_wm_pipe_parameters()
3126 struct intel_plane *intel_plane = to_intel_plane(plane); in skl_compute_wm_pipe_parameters()
3129 plane->type == DRM_PLANE_TYPE_OVERLAY) in skl_compute_wm_pipe_parameters()
3130 p->plane[i++] = intel_plane->wm; in skl_compute_wm_pipe_parameters()
3225 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); in skl_compute_wm_level()
3228 p, &p->plane[i], in skl_compute_wm_level()
3235 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]); in skl_compute_wm_level()
3237 &p->plane[PLANE_CURSOR], in skl_compute_wm_level()
3312 r->plane[pipe][i][level] = temp; in skl_compute_wm_results()
3323 r->plane[pipe][PLANE_CURSOR][level] = temp; in skl_compute_wm_results()
3376 new->plane[pipe][i][level]); in skl_write_wm_values()
3378 new->plane[pipe][PLANE_CURSOR][level]); in skl_write_wm_values()
3389 &new->ddb.plane[pipe][i]); in skl_write_wm_values()
3396 &new->ddb.plane[pipe][PLANE_CURSOR]); in skl_write_wm_values()
3427 int plane; in skl_wm_flush_pipe() local
3431 for_each_plane(dev_priv, pipe, plane) { in skl_wm_flush_pipe()
3432 I915_WRITE(PLANE_SURF(pipe, plane), in skl_wm_flush_pipe()
3433 I915_READ(PLANE_SURF(pipe, plane))); in skl_wm_flush_pipe()
3607 memset(watermarks->plane[pipe], 0, in skl_clear_wm()
3615 memset(&watermarks->ddb.plane[pipe], 0, in skl_clear_wm()
3619 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0, in skl_clear_wm()
3658 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc, in skl_update_sprite_wm() argument
3662 struct intel_plane *intel_plane = to_intel_plane(plane); in skl_update_sprite_wm()
3663 struct drm_framebuffer *fb = plane->state->fb; in skl_update_sprite_wm()
3674 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size; in skl_update_sprite_wm()
3677 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0; in skl_update_sprite_wm()
3685 intel_plane->wm.rotation = plane->state->rotation; in skl_update_sprite_wm()
3737 ilk_update_sprite_wm(struct drm_plane *plane, in ilk_update_sprite_wm() argument
3742 struct drm_device *dev = plane->dev; in ilk_update_sprite_wm()
3743 struct intel_plane *intel_plane = to_intel_plane(plane); in ilk_update_sprite_wm()
3819 hw->plane[pipe][i][level] = in skl_pipe_wm_get_hw_state()
3821 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level)); in skl_pipe_wm_get_hw_state()
3837 temp = hw->plane[pipe][i][level]; in skl_pipe_wm_get_hw_state()
3841 temp = hw->plane[pipe][PLANE_CURSOR][level]; in skl_pipe_wm_get_hw_state()
3914 #define _FW_WM(value, plane) \ argument
3915 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3916 #define _FW_WM_VLV(value, plane) \ argument
3917 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3939 wm->sr.plane = _FW_WM(tmp, SR); in vlv_read_wm_values()
3966 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; in vlv_read_wm_values()
3982 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; in vlv_read_wm_values()
3999 struct intel_plane *plane; in vlv_wm_get_hw_state() local
4005 for_each_intel_plane(dev, plane) { in vlv_wm_get_hw_state()
4006 switch (plane->base.type) { in vlv_wm_get_hw_state()
4009 plane->wm.fifo_size = 63; in vlv_wm_get_hw_state()
4012 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0); in vlv_wm_get_hw_state()
4015 sprite = plane->plane; in vlv_wm_get_hw_state()
4016 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1); in vlv_wm_get_hw_state()
4064 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); in vlv_wm_get_hw_state()
4137 void intel_update_sprite_watermarks(struct drm_plane *plane, in intel_update_sprite_watermarks() argument
4144 struct drm_i915_private *dev_priv = plane->dev->dev_private; in intel_update_sprite_watermarks()
4147 dev_priv->display.update_sprite_wm(plane, crtc, in intel_update_sprite_watermarks()