Lines Matching refs:CACHELINE_BYTES
220 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in intel_emit_post_sync_nonzero_flush()
257 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in gen6_render_ring_flush()
330 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in gen7_render_ring_flush()
415 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in gen8_render_ring_flush()
1466 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in pc_render_add_request()
1488 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ in pc_render_add_request()
1490 scratch_addr += 2 * CACHELINE_BYTES; in pc_render_add_request()
1492 scratch_addr += 2 * CACHELINE_BYTES; in pc_render_add_request()
1494 scratch_addr += 2 * CACHELINE_BYTES; in pc_render_add_request()
1496 scratch_addr += 2 * CACHELINE_BYTES; in pc_render_add_request()
2098 ring->effective_size -= 2 * CACHELINE_BYTES; in intel_engine_create_ringbuffer()
2411 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); in intel_ring_cacheline_align()
2417 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; in intel_ring_cacheline_align()