479 	I915_WRITE(HWS_PGA, addr);  in ring_setup_phys_status_page()
518 	I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);  in intel_ring_setup_status_page()
534 		I915_WRITE(reg,  in intel_ring_setup_status_page()
914 	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |  in gen9_init_workarounds()
918 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |  in gen9_init_workarounds()
1045 		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |  in skl_init_workarounds()
1049 		I915_WRITE(FF_SLICE_CS_CHICKEN2,  in skl_init_workarounds()
1058 		I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |  in skl_init_workarounds()
1063 		I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |  in skl_init_workarounds()
1113 		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);  in bxt_init_workarounds()
1117 		I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &  in bxt_init_workarounds()
1169 		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));  in init_render_ring()
1178 		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));  in init_render_ring()
1183 		I915_WRITE(GFX_MODE,  in init_render_ring()
1188 		I915_WRITE(GFX_MODE_GEN7,  in init_render_ring()
1198 		I915_WRITE(CACHE_MODE_0,  in init_render_ring()
1203 		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));  in init_render_ring()
1593 		I915_WRITE(IMR, dev_priv->irq_mask);  in i9xx_ring_get_irq()
1611 		I915_WRITE(IMR, dev_priv->irq_mask);  in i9xx_ring_put_irq()
2436 		I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);  in intel_ring_init_seqno()
2437 		I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);  in intel_ring_init_seqno()
2439 			I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);  in intel_ring_init_seqno()
2456 	I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,  in gen6_bsd_ring_write_tail()
2475 	I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,  in gen6_bsd_ring_write_tail()