95 	return I915_READ(HSW_PWR_WELL_DRIVER) ==  in hsw_power_well_enabled()
261 	tmp = I915_READ(HSW_PWR_WELL_DRIVER);  in hsw_set_power_well()
272 			if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &  in hsw_set_power_well()
387 	WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),  in assert_can_enable_dc9()
389 	WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,  in assert_can_enable_dc9()
391 	WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");  in assert_can_enable_dc9()
406 	WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),  in assert_can_disable_dc9()
408 	WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,  in assert_can_disable_dc9()
428 	val = I915_READ(DC_STATE_EN);  in bxt_enable_dc9()
442 	val = I915_READ(DC_STATE_EN);  in bxt_disable_dc9()
454 	val = I915_READ(DC_STATE_DEBUG);  in gen9_set_dc_state_debugmask_memory_up()
472 	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),  in assert_can_enable_dc5()
506 	val = I915_READ(DC_STATE_EN);  in gen9_enable_dc5()
521 	val = I915_READ(DC_STATE_EN);  in gen9_disable_dc5()
533 	WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,  in assert_can_enable_dc6()
535 	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),  in assert_can_enable_dc6()
551 	WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),  in assert_can_disable_dc6()
565 	val = I915_READ(DC_STATE_EN);  in skl_enable_dc6()
580 	val = I915_READ(DC_STATE_EN);  in skl_disable_dc6()
594 	tmp = I915_READ(HSW_PWR_WELL_DRIVER);  in skl_set_power_well()
595 	fuse_status = I915_READ(SKL_FUSE_STATUS);  in skl_set_power_well()
599 		if (wait_for((I915_READ(SKL_FUSE_STATUS) &  in skl_set_power_well()
630 				!I915_READ(HSW_PWR_WELL_BIOS),  in skl_set_power_well()
653 			if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &  in skl_set_power_well()
694 			if (wait_for((I915_READ(SKL_FUSE_STATUS) &  in skl_set_power_well()
698 			if (wait_for((I915_READ(SKL_FUSE_STATUS) &  in skl_set_power_well()
717 	if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)  in hsw_power_well_sync_hw()
739 	return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;  in skl_power_well_enabled()
877 		u32 val = I915_READ(DPLL(pipe));  in vlv_display_power_well_init()
952 	I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);  in vlv_dpio_cmn_power_well_enable()
966 	I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);  in vlv_dpio_cmn_power_well_disable()
1044 		    (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)  in assert_chv_phy_status()
1087 	if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))  in assert_chv_phy_status()
1118 	if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))  in chv_dpio_cmn_power_well_enable()
1954 		uint32_t status = I915_READ(DPLL(PIPE_A));  in chv_phy_control_init()
1985 		uint32_t status = I915_READ(DPIO_PHY_STATUS);  in chv_phy_control_init()
2022 	    I915_READ(DPIO_CTL) & DPIO_CMNRST)  in vlv_cmnlane_wa()