267 			I915_WRITE(HSW_PWR_WELL_DRIVER,  in hsw_set_power_well()
280 			I915_WRITE(HSW_PWR_WELL_DRIVER, 0);  in hsw_set_power_well()
430 	I915_WRITE(DC_STATE_EN, val);  in bxt_enable_dc9()
444 	I915_WRITE(DC_STATE_EN, val);  in bxt_disable_dc9()
457 		I915_WRITE(DC_STATE_DEBUG, val);  in gen9_set_dc_state_debugmask_memory_up()
509 	I915_WRITE(DC_STATE_EN, val);  in gen9_enable_dc5()
523 	I915_WRITE(DC_STATE_EN, val);  in gen9_disable_dc5()
568 	I915_WRITE(DC_STATE_EN, val);  in skl_enable_dc6()
582 	I915_WRITE(DC_STATE_EN, val);  in skl_disable_dc6()
648 			I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);  in skl_set_power_well()
666 				I915_WRITE(HSW_PWR_WELL_DRIVER,	tmp & ~req_mask);  in skl_set_power_well()
718 		I915_WRITE(HSW_PWR_WELL_BIOS, 0);  in hsw_power_well_sync_hw()
748 	I915_WRITE(HSW_PWR_WELL_BIOS, 0);  in skl_power_well_sync_hw()
883 		I915_WRITE(DPLL(pipe), val);  in vlv_display_power_well_init()
952 	I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);  in vlv_dpio_cmn_power_well_enable()
966 	I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);  in vlv_dpio_cmn_power_well_disable()
1147 	I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);  in chv_dpio_cmn_power_well_enable()
1173 	I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);  in chv_dpio_cmn_power_well_disable()
1266 	I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);  in chv_phy_powergate_ch()
1297 	I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);  in chv_phy_powergate_lanes()
2006 	I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);  in chv_phy_control_init()