207 static inline uint32_t REG_MDP5_MDP(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); }  in REG_MDP5_MDP()
209 static inline uint32_t REG_MDP5_MDP_HW_VERSION(uint32_t i0) { return 0x00000000 + __offset_MDP(i0);…  in REG_MDP5_MDP_HW_VERSION()
229 static inline uint32_t REG_MDP5_MDP_DISP_INTF_SEL(uint32_t i0) { return 0x00000004 + __offset_MDP(i…  in REG_MDP5_MDP_DISP_INTF_SEL()
255 static inline uint32_t REG_MDP5_MDP_INTR_EN(uint32_t i0) { return 0x00000010 + __offset_MDP(i0); }  in REG_MDP5_MDP_INTR_EN()
257 static inline uint32_t REG_MDP5_MDP_INTR_STATUS(uint32_t i0) { return 0x00000014 + __offset_MDP(i0)…  in REG_MDP5_MDP_INTR_STATUS()
259 static inline uint32_t REG_MDP5_MDP_INTR_CLEAR(uint32_t i0) { return 0x00000018 + __offset_MDP(i0);…  in REG_MDP5_MDP_INTR_CLEAR()
261 static inline uint32_t REG_MDP5_MDP_HIST_INTR_EN(uint32_t i0) { return 0x0000001c + __offset_MDP(i0…  in REG_MDP5_MDP_HIST_INTR_EN()
263 static inline uint32_t REG_MDP5_MDP_HIST_INTR_STATUS(uint32_t i0) { return 0x00000020 + __offset_MD…  in REG_MDP5_MDP_HIST_INTR_STATUS()
265 static inline uint32_t REG_MDP5_MDP_HIST_INTR_CLEAR(uint32_t i0) { return 0x00000024 + __offset_MDP…  in REG_MDP5_MDP_HIST_INTR_CLEAR()
267 static inline uint32_t REG_MDP5_MDP_SPARE_0(uint32_t i0) { return 0x00000028 + __offset_MDP(i0); }  in REG_MDP5_MDP_SPARE_0()
270 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W(uint32_t i0, uint32_t i1) { return 0x00000080 + __o…  in REG_MDP5_MDP_SMP_ALLOC_W()
272 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W_REG(uint32_t i0, uint32_t i1) { return 0x00000080 +…  in REG_MDP5_MDP_SMP_ALLOC_W_REG()
292 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R(uint32_t i0, uint32_t i1) { return 0x00000130 + __o…  in REG_MDP5_MDP_SMP_ALLOC_R()
294 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R_REG(uint32_t i0, uint32_t i1) { return 0x00000130 +…  in REG_MDP5_MDP_SMP_ALLOC_R_REG()
324 static inline uint32_t REG_MDP5_MDP_IGC(uint32_t i0, enum mdp5_igc_type i1) { return 0x00000000 + _…  in REG_MDP5_MDP_IGC()
326 static inline uint32_t REG_MDP5_MDP_IGC_LUT(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { retu…  in REG_MDP5_MDP_IGC_LUT()
328 static inline uint32_t REG_MDP5_MDP_IGC_LUT_REG(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { …  in REG_MDP5_MDP_IGC_LUT_REG()
340 static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_EN(uint32_t i0) { return 0x000002f4 + __offset_MDP(i0…  in REG_MDP5_MDP_SPLIT_DPL_EN()
342 static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_UPPER(uint32_t i0) { return 0x000002f8 + __offset_MDP…  in REG_MDP5_MDP_SPLIT_DPL_UPPER()
348 static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_LOWER(uint32_t i0) { return 0x000003f0 + __offset_MDP…  in REG_MDP5_MDP_SPLIT_DPL_LOWER()
365 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }  in REG_MDP5_CTL()
379 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_…  in REG_MDP5_CTL_LAYER()
381 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __off…  in REG_MDP5_CTL_LAYER_REG()
445 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }  in REG_MDP5_CTL_OP()
467 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }  in REG_MDP5_CTL_FLUSH()
498 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }  in REG_MDP5_CTL_START()
500 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }  in REG_MDP5_CTL_PACK_3D()
514 static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __off…  in REG_MDP5_CTL_LAYER_EXT()
516 static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + _…  in REG_MDP5_CTL_LAYER_EXT_REG()
556 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }  in REG_MDP5_PIPE()
558 static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE…  in REG_MDP5_PIPE_OP_MODE()
573 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offse…  in REG_MDP5_PIPE_HIST_CTL_BASE()
575 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offse…  in REG_MDP5_PIPE_HIST_LUT_BASE()
577 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offse…  in REG_MDP5_PIPE_HIST_LUT_SWAP()
579 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0()
593 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1()
607 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2()
621 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3()
635 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4()
643 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP5_PIPE_CSC_1_PRE_CLAMP()
645 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0…  in REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG()
659 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00…  in REG_MDP5_PIPE_CSC_1_POST_CLAMP()
661 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return …  in REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG()
675 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000…  in REG_MDP5_PIPE_CSC_1_PRE_BIAS()
677 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x…  in REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG()
685 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP5_PIPE_CSC_1_POST_BIAS()
687 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0…  in REG_MDP5_PIPE_CSC_1_POST_BIAS_REG()
695 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIP…  in REG_MDP5_PIPE_SRC_SIZE()
709 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset…  in REG_MDP5_PIPE_SRC_IMG_SIZE()
723 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(…  in REG_MDP5_PIPE_SRC_XY()
737 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIP…  in REG_MDP5_PIPE_OUT_SIZE()
751 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(…  in REG_MDP5_PIPE_OUT_XY()
765 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PI…  in REG_MDP5_PIPE_SRC0_ADDR()
767 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PI…  in REG_MDP5_PIPE_SRC1_ADDR()
769 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PI…  in REG_MDP5_PIPE_SRC2_ADDR()
771 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PI…  in REG_MDP5_PIPE_SRC3_ADDR()
773 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset…  in REG_MDP5_PIPE_SRC_STRIDE_A()
787 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset…  in REG_MDP5_PIPE_SRC_STRIDE_B()
801 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __of…  in REG_MDP5_PIPE_STILE_FRAME_SIZE()
803 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_P…  in REG_MDP5_PIPE_SRC_FORMAT()
857 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_P…  in REG_MDP5_PIPE_SRC_UNPACK()
883 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_…  in REG_MDP5_PIPE_SRC_OP_MODE()
900 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __…  in REG_MDP5_PIPE_SRC_CONSTANT_COLOR()
902 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset…  in REG_MDP5_PIPE_FETCH_CONFIG()
904 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PI…  in REG_MDP5_PIPE_VC1_RANGE()
906 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_0()
908 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_1()
910 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_2()
912 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __…  in REG_MDP5_PIPE_SRC_ADDR_SW_STATUS()
914 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __o…  in REG_MDP5_PIPE_CURRENT_SRC0_ADDR()
916 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __o…  in REG_MDP5_PIPE_CURRENT_SRC1_ADDR()
918 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __o…  in REG_MDP5_PIPE_CURRENT_SRC2_ADDR()
920 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __o…  in REG_MDP5_PIPE_CURRENT_SRC3_ADDR()
922 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_P…  in REG_MDP5_PIPE_DECIMATION()
945 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { re…  in REG_MDP5_PIPE_SW_PIX_EXT()
947 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) {…  in REG_MDP5_PIPE_SW_PIX_EXT_LR()
973 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) {…  in REG_MDP5_PIPE_SW_PIX_EXT_TB()
999 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_ty…  in REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS()
1013 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset…  in REG_MDP5_PIPE_SCALE_CONFIG()
1053 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __…  in REG_MDP5_PIPE_SCALE_PHASE_STEP_X()
1055 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __…  in REG_MDP5_PIPE_SCALE_PHASE_STEP_Y()
1057 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 +…  in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X()
1059 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c +…  in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y()
1061 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __…  in REG_MDP5_PIPE_SCALE_INIT_PHASE_X()
1063 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __…  in REG_MDP5_PIPE_SCALE_INIT_PHASE_Y()
1077 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }  in REG_MDP5_LM()
1079 static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i…  in REG_MDP5_LM_BLEND_COLOR_OUT()
1085 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }  in REG_MDP5_LM_OUT_SIZE()
1099 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0…  in REG_MDP5_LM_BORDER_COLOR_0()
1101 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0…  in REG_MDP5_LM_BORDER_COLOR_1()
1116 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_L…  in REG_MDP5_LM_BLEND()
1118 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __…  in REG_MDP5_LM_BLEND_OP_MODE()
1140 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + _…  in REG_MDP5_LM_BLEND_FG_ALPHA()
1142 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + _…  in REG_MDP5_LM_BLEND_BG_ALPHA()
1144 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_FG_TRANSP_LOW0()
1146 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_FG_TRANSP_LOW1()
1148 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0()
1150 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1()
1152 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_BG_TRANSP_LOW0()
1154 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_BG_TRANSP_LOW1()
1156 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0()
1158 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1()
1160 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i…  in REG_MDP5_LM_CURSOR_IMG_SIZE()
1174 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }  in REG_MDP5_LM_CURSOR_SIZE()
1188 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }  in REG_MDP5_LM_CURSOR_XY()
1202 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0)…  in REG_MDP5_LM_CURSOR_STRIDE()
1210 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0)…  in REG_MDP5_LM_CURSOR_FORMAT()
1218 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(…  in REG_MDP5_LM_CURSOR_BASE_ADDR()
1220 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i…  in REG_MDP5_LM_CURSOR_START_XY()
1234 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_…  in REG_MDP5_LM_CURSOR_BLEND_CONFIG()
1244 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_L…  in REG_MDP5_LM_CURSOR_BLEND_PARAM()
1246 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __of…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0()
1248 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __of…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1()
1250 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __o…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0()
1252 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __o…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1()
1254 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }  in REG_MDP5_LM_GC_LUT_BASE()
1266 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }  in REG_MDP5_DSPP()
1268 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }  in REG_MDP5_DSPP_OP_MODE()
1285 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0);…  in REG_MDP5_DSPP_PCC_BASE()
1287 static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(…  in REG_MDP5_DSPP_DITHER_DEPTH()
1289 static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP…  in REG_MDP5_DSPP_HIST_CTL_BASE()
1291 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP…  in REG_MDP5_DSPP_HIST_LUT_BASE()
1293 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP…  in REG_MDP5_DSPP_HIST_LUT_SWAP()
1295 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }  in REG_MDP5_DSPP_PA_BASE()
1297 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0…  in REG_MDP5_DSPP_GAMUT_BASE()
1299 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }  in REG_MDP5_DSPP_GC_BASE()
1311 static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }  in REG_MDP5_PP()
1313 static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0)…  in REG_MDP5_PP_TEAR_CHECK_EN()
1315 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP…  in REG_MDP5_PP_SYNC_CONFIG_VSYNC()
1325 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_P…  in REG_MDP5_PP_SYNC_CONFIG_HEIGHT()
1327 static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0);…  in REG_MDP5_PP_SYNC_WRCOUNT()
1341 static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0…  in REG_MDP5_PP_VSYNC_INIT_VAL()
1343 static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0)…  in REG_MDP5_PP_INT_COUNT_VAL()
1357 static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); }  in REG_MDP5_PP_SYNC_THRESH()
1371 static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); }  in REG_MDP5_PP_START_POS()
1373 static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); }  in REG_MDP5_PP_RD_PTR_IRQ()
1375 static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); }  in REG_MDP5_PP_WR_PTR_IRQ()
1377 static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0…  in REG_MDP5_PP_OUT_LINE_COUNT()
1379 static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0)…  in REG_MDP5_PP_PP_LINE_COUNT()
1381 static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_P…  in REG_MDP5_PP_AUTOREFRESH_CONFIG()
1383 static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); }  in REG_MDP5_PP_FBC_MODE()
1385 static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0…  in REG_MDP5_PP_FBC_BUDGET_CTL()
1387 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0…  in REG_MDP5_PP_FBC_LOSSY_MODE()
1402 static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }  in REG_MDP5_WB()
1404 static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }  in REG_MDP5_WB_DST_FORMAT()
1471 static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); }  in REG_MDP5_WB_DST_OP_MODE()
1525 static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(…  in REG_MDP5_WB_DST_PACK_PATTERN()
1551 static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); }  in REG_MDP5_WB_DST0_ADDR()
1553 static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); }  in REG_MDP5_WB_DST1_ADDR()
1555 static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); }  in REG_MDP5_WB_DST2_ADDR()
1557 static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); }  in REG_MDP5_WB_DST3_ADDR()
1559 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0);…  in REG_MDP5_WB_DST_YSTRIDE0()
1573 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0);…  in REG_MDP5_WB_DST_YSTRIDE1()
1587 static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_…  in REG_MDP5_WB_DST_DITHER_BITDEPTH()
1589 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_W…  in REG_MDP5_WB_DITHER_MATRIX_ROW0()
1591 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_W…  in REG_MDP5_WB_DITHER_MATRIX_ROW1()
1593 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_W…  in REG_MDP5_WB_DITHER_MATRIX_ROW2()
1595 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_W…  in REG_MDP5_WB_DITHER_MATRIX_ROW3()
1597 static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(…  in REG_MDP5_WB_DST_WRITE_CONFIG()
1599 static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB…  in REG_MDP5_WB_ROTATION_DNSCALER()
1601 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset…  in REG_MDP5_WB_N16_INIT_PHASE_X_0_3()
1603 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset…  in REG_MDP5_WB_N16_INIT_PHASE_X_1_2()
1605 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset…  in REG_MDP5_WB_N16_INIT_PHASE_Y_0_3()
1607 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset…  in REG_MDP5_WB_N16_INIT_PHASE_Y_1_2()
1609 static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); }  in REG_MDP5_WB_OUT_SIZE()
1623 static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0)…  in REG_MDP5_WB_ALPHA_X_VALUE()
1625 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_0()
1639 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_1()
1653 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_2()
1667 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_3()
1681 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_4()
1689 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 …  in REG_MDP5_WB_CSC_COMP_PRECLAMP()
1691 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_WB_CSC_COMP_PRECLAMP_REG()
1705 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280…  in REG_MDP5_WB_CSC_COMP_POSTCLAMP()
1707 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x0000…  in REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG()
1721 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c +…  in REG_MDP5_WB_CSC_COMP_PREBIAS()
1723 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x000002…  in REG_MDP5_WB_CSC_COMP_PREBIAS_REG()
1731 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 …  in REG_MDP5_WB_CSC_COMP_POSTBIAS()
1733 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_WB_CSC_COMP_POSTBIAS_REG()
1752 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }  in REG_MDP5_INTF()
1754 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_I…  in REG_MDP5_INTF_TIMING_ENGINE_EN()
1756 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }  in REG_MDP5_INTF_CONFIG()
1758 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0)…  in REG_MDP5_INTF_HSYNC_CTL()
1772 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_IN…  in REG_MDP5_INTF_VSYNC_PERIOD_F0()
1774 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_IN…  in REG_MDP5_INTF_VSYNC_PERIOD_F1()
1776 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(…  in REG_MDP5_INTF_VSYNC_LEN_F0()
1778 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(…  in REG_MDP5_INTF_VSYNC_LEN_F1()
1780 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_…  in REG_MDP5_INTF_DISPLAY_VSTART_F0()
1782 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_…  in REG_MDP5_INTF_DISPLAY_VSTART_F1()
1784 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_IN…  in REG_MDP5_INTF_DISPLAY_VEND_F0()
1786 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_IN…  in REG_MDP5_INTF_DISPLAY_VEND_F1()
1788 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_I…  in REG_MDP5_INTF_ACTIVE_VSTART_F0()
1797 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_I…  in REG_MDP5_INTF_ACTIVE_VSTART_F1()
1805 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INT…  in REG_MDP5_INTF_ACTIVE_VEND_F0()
1807 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INT…  in REG_MDP5_INTF_ACTIVE_VEND_F1()
1809 static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(…  in REG_MDP5_INTF_DISPLAY_HCTL()
1823 static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i…  in REG_MDP5_INTF_ACTIVE_HCTL()
1838 static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(…  in REG_MDP5_INTF_BORDER_COLOR()
1840 static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_IN…  in REG_MDP5_INTF_UNDERFLOW_COLOR()
1842 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0…  in REG_MDP5_INTF_HSYNC_SKEW()
1844 static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(…  in REG_MDP5_INTF_POLARITY_CTL()
1849 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0);…  in REG_MDP5_INTF_TEST_CTL()
1851 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0)…  in REG_MDP5_INTF_TP_COLOR0()
1853 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0)…  in REG_MDP5_INTF_TP_COLOR1()
1855 static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __o…  in REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN()
1857 static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(…  in REG_MDP5_INTF_PANEL_FORMAT()
1859 static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offse…  in REG_MDP5_INTF_FRAME_LINE_COUNT_EN()
1861 static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i…  in REG_MDP5_INTF_FRAME_COUNT()
1863 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0…  in REG_MDP5_INTF_LINE_COUNT()
1865 static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_I…  in REG_MDP5_INTF_DEFLICKER_CONFIG()
1867 static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __off…  in REG_MDP5_INTF_DEFLICKER_STRNG_COEFF()
1869 static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offs…  in REG_MDP5_INTF_DEFLICKER_WEAK_COEFF()
1871 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0…  in REG_MDP5_INTF_TPG_ENABLE()
1873 static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_I…  in REG_MDP5_INTF_TPG_MAIN_CONTROL()
1875 static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_I…  in REG_MDP5_INTF_TPG_VIDEO_CONFIG()
1877 static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offs…  in REG_MDP5_INTF_TPG_COMPONENT_LIMITS()
1879 static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF…  in REG_MDP5_INTF_TPG_RECTANGLE()
1881 static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_…  in REG_MDP5_INTF_TPG_INITIAL_VALUE()
1883 static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 +…  in REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME()
1885 static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_IN…  in REG_MDP5_INTF_TPG_RGB_MAPPING()
1895 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }  in REG_MDP5_AD()
1897 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }  in REG_MDP5_AD_BYPASS()
1899 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }  in REG_MDP5_AD_CTRL_0()
1901 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }  in REG_MDP5_AD_CTRL_1()
1903 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }  in REG_MDP5_AD_FRAME_SIZE()
1905 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }  in REG_MDP5_AD_CON_CTRL_0()
1907 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }  in REG_MDP5_AD_CON_CTRL_1()
1909 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }  in REG_MDP5_AD_STR_MAN()
1911 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }  in REG_MDP5_AD_VAR()
1913 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }  in REG_MDP5_AD_DITH()
1915 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }  in REG_MDP5_AD_DITH_CTRL()
1917 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }  in REG_MDP5_AD_AMP_LIM()
1919 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }  in REG_MDP5_AD_SLOPE()
1921 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }  in REG_MDP5_AD_BW_LVL()
1923 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }  in REG_MDP5_AD_LOGO_POS()
1925 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }  in REG_MDP5_AD_LUT_FI()
1927 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }  in REG_MDP5_AD_LUT_CC()
1929 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }  in REG_MDP5_AD_STR_LIM()
1931 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }  in REG_MDP5_AD_CALIB_AB()
1933 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }  in REG_MDP5_AD_CALIB_CD()
1935 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }  in REG_MDP5_AD_MODE_SEL()
1937 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }  in REG_MDP5_AD_TFILT_CTRL()
1939 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }  in REG_MDP5_AD_BL_MINMAX()
1941 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }  in REG_MDP5_AD_BL()
1943 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }  in REG_MDP5_AD_BL_MAX()
1945 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }  in REG_MDP5_AD_AL()
1947 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }  in REG_MDP5_AD_AL_MIN()
1949 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }  in REG_MDP5_AD_AL_FILT()
1951 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }  in REG_MDP5_AD_CFG_BUF()
1953 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }  in REG_MDP5_AD_LUT_AL()
1955 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }  in REG_MDP5_AD_TARG_STR()
1957 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }  in REG_MDP5_AD_START_CALC()
1959 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }  in REG_MDP5_AD_STR_OUT()
1961 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }  in REG_MDP5_AD_BL_OUT()
1963 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }  in REG_MDP5_AD_CALC_DONE()