40 	struct nv50_bar *bar = nv50_bar(base);  in nv50_bar_umap()  local
41 	return nvkm_vm_get(bar->bar1_vm, size, type, NV_MEM_ACCESS_RW, vma);  in nv50_bar_umap()
47 	struct nv50_bar *bar = nv50_bar(base);  in nv50_bar_flush()  local
48 	struct nvkm_device *device = bar->base.subdev.device;  in nv50_bar_flush()
50 	spin_lock_irqsave(&bar->base.lock, flags);  in nv50_bar_flush()
56 	spin_unlock_irqrestore(&bar->base.lock, flags);  in nv50_bar_flush()
62 	struct nv50_bar *bar = nv50_bar(base);  in nv50_bar_oneinit()  local
63 	struct nvkm_device *device = bar->base.subdev.device;  in nv50_bar_oneinit()
70 	ret = nvkm_gpuobj_new(device, 0x20000, 0, false, NULL, &bar->mem);  in nv50_bar_oneinit()
74 	ret = nvkm_gpuobj_new(device, bar->pgd_addr, 0, false, bar->mem,  in nv50_bar_oneinit()
75 			      &bar->pad);  in nv50_bar_oneinit()
79 	ret = nvkm_gpuobj_new(device, 0x4000, 0, false, bar->mem, &bar->pgd);  in nv50_bar_oneinit()
97 	ret = nvkm_vm_ref(vm, &bar->bar3_vm, bar->pgd);  in nv50_bar_oneinit()
102 	ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar3);  in nv50_bar_oneinit()
106 	nvkm_kmap(bar->bar3);  in nv50_bar_oneinit()
107 	nvkm_wo32(bar->bar3, 0x00, 0x7fc00000);  in nv50_bar_oneinit()
108 	nvkm_wo32(bar->bar3, 0x04, lower_32_bits(limit));  in nv50_bar_oneinit()
109 	nvkm_wo32(bar->bar3, 0x08, lower_32_bits(start));  in nv50_bar_oneinit()
110 	nvkm_wo32(bar->bar3, 0x0c, upper_32_bits(limit) << 24 |  in nv50_bar_oneinit()
112 	nvkm_wo32(bar->bar3, 0x10, 0x00000000);  in nv50_bar_oneinit()
113 	nvkm_wo32(bar->bar3, 0x14, 0x00000000);  in nv50_bar_oneinit()
114 	nvkm_done(bar->bar3);  in nv50_bar_oneinit()
126 	ret = nvkm_vm_ref(vm, &bar->bar1_vm, bar->pgd);  in nv50_bar_oneinit()
131 	ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar1);  in nv50_bar_oneinit()
135 	nvkm_kmap(bar->bar1);  in nv50_bar_oneinit()
136 	nvkm_wo32(bar->bar1, 0x00, 0x7fc00000);  in nv50_bar_oneinit()
137 	nvkm_wo32(bar->bar1, 0x04, lower_32_bits(limit));  in nv50_bar_oneinit()
138 	nvkm_wo32(bar->bar1, 0x08, lower_32_bits(start));  in nv50_bar_oneinit()
139 	nvkm_wo32(bar->bar1, 0x0c, upper_32_bits(limit) << 24 |  in nv50_bar_oneinit()
141 	nvkm_wo32(bar->bar1, 0x10, 0x00000000);  in nv50_bar_oneinit()
142 	nvkm_wo32(bar->bar1, 0x14, 0x00000000);  in nv50_bar_oneinit()
143 	nvkm_done(bar->bar1);  in nv50_bar_oneinit()
150 	struct nv50_bar *bar = nv50_bar(base);  in nv50_bar_init()  local
151 	struct nvkm_device *device = bar->base.subdev.device;  in nv50_bar_init()
163 	nvkm_wr32(device, 0x001704, 0x00000000 | bar->mem->addr >> 12);  in nv50_bar_init()
164 	nvkm_wr32(device, 0x001704, 0x40000000 | bar->mem->addr >> 12);  in nv50_bar_init()
165 	nvkm_wr32(device, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4);  in nv50_bar_init()
166 	nvkm_wr32(device, 0x00170c, 0x80000000 | bar->bar3->node->offset >> 4);  in nv50_bar_init()
175 	struct nv50_bar *bar = nv50_bar(base);  in nv50_bar_dtor()  local
176 	nvkm_gpuobj_del(&bar->bar1);  in nv50_bar_dtor()
177 	nvkm_vm_ref(NULL, &bar->bar1_vm, bar->pgd);  in nv50_bar_dtor()
178 	nvkm_gpuobj_del(&bar->bar3);  in nv50_bar_dtor()
179 	if (bar->bar3_vm) {  in nv50_bar_dtor()
180 		nvkm_memory_del(&bar->bar3_vm->pgt[0].mem[0]);  in nv50_bar_dtor()
181 		nvkm_vm_ref(NULL, &bar->bar3_vm, bar->pgd);  in nv50_bar_dtor()
183 	nvkm_gpuobj_del(&bar->pgd);  in nv50_bar_dtor()
184 	nvkm_gpuobj_del(&bar->pad);  in nv50_bar_dtor()
185 	nvkm_gpuobj_del(&bar->mem);  in nv50_bar_dtor()
186 	return bar;  in nv50_bar_dtor()
193 	struct nv50_bar *bar;  in nv50_bar_new_()  local
194 	if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL)))  in nv50_bar_new_()
196 	nvkm_bar_ctor(func, device, index, &bar->base);  in nv50_bar_new_()
197 	bar->pgd_addr = pgd_addr;  in nv50_bar_new_()
198 	*pbar = &bar->base;  in nv50_bar_new_()