Lines Matching refs:clk
125 gk20a_pllg_read_mnp(struct gk20a_clk *clk) in gk20a_pllg_read_mnp() argument
127 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_read_mnp()
131 clk->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); in gk20a_pllg_read_mnp()
132 clk->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); in gk20a_pllg_read_mnp()
133 clk->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); in gk20a_pllg_read_mnp()
137 gk20a_pllg_calc_rate(struct gk20a_clk *clk) in gk20a_pllg_calc_rate() argument
142 rate = clk->parent_rate * clk->n; in gk20a_pllg_calc_rate()
143 divider = clk->m * pl_to_div[clk->pl]; in gk20a_pllg_calc_rate()
150 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) in gk20a_pllg_calc_mnp() argument
152 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_pllg_calc_mnp()
164 ref_clk_f = clk->parent_rate / MHZ; in gk20a_pllg_calc_mnp()
166 max_vco_f = clk->params->max_vco; in gk20a_pllg_calc_mnp()
167 min_vco_f = clk->params->min_vco; in gk20a_pllg_calc_mnp()
168 best_m = clk->params->max_m; in gk20a_pllg_calc_mnp()
169 best_n = clk->params->min_n; in gk20a_pllg_calc_mnp()
170 best_pl = clk->params->min_pl; in gk20a_pllg_calc_mnp()
178 high_pl = min(high_pl, clk->params->max_pl); in gk20a_pllg_calc_mnp()
179 high_pl = max(high_pl, clk->params->min_pl); in gk20a_pllg_calc_mnp()
183 low_pl = min(low_pl, clk->params->max_pl); in gk20a_pllg_calc_mnp()
184 low_pl = max(low_pl, clk->params->min_pl); in gk20a_pllg_calc_mnp()
206 for (m = clk->params->min_m; m <= clk->params->max_m; m++) { in gk20a_pllg_calc_mnp()
209 if (u_f < clk->params->min_u) in gk20a_pllg_calc_mnp()
211 if (u_f > clk->params->max_u) in gk20a_pllg_calc_mnp()
217 if (n > clk->params->max_n) in gk20a_pllg_calc_mnp()
221 if (n < clk->params->min_n) in gk20a_pllg_calc_mnp()
223 if (n > clk->params->max_n) in gk20a_pllg_calc_mnp()
255 clk->m = best_m; in gk20a_pllg_calc_mnp()
256 clk->n = best_n; in gk20a_pllg_calc_mnp()
257 clk->pl = best_pl; in gk20a_pllg_calc_mnp()
259 target_freq = gk20a_pllg_calc_rate(clk) / MHZ; in gk20a_pllg_calc_mnp()
263 target_freq, clk->m, clk->n, clk->pl, pl_to_div[clk->pl]); in gk20a_pllg_calc_mnp()
268 gk20a_pllg_slide(struct gk20a_clk *clk, u32 n) in gk20a_pllg_slide() argument
270 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_pllg_slide()
327 _gk20a_pllg_enable(struct gk20a_clk *clk) in _gk20a_pllg_enable() argument
329 struct nvkm_device *device = clk->base.subdev.device; in _gk20a_pllg_enable()
335 _gk20a_pllg_disable(struct gk20a_clk *clk) in _gk20a_pllg_disable() argument
337 struct nvkm_device *device = clk->base.subdev.device; in _gk20a_pllg_disable()
343 _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide) in _gk20a_pllg_program_mnp() argument
345 struct nvkm_subdev *subdev = &clk->base.subdev; in _gk20a_pllg_program_mnp()
357 if (allow_slide && clk->m == m_old && clk->pl == pl_old && in _gk20a_pllg_program_mnp()
359 return gk20a_pllg_slide(clk, clk->n); in _gk20a_pllg_program_mnp()
363 n_lo = DIV_ROUND_UP(m_old * clk->params->min_vco, in _gk20a_pllg_program_mnp()
364 clk->parent_rate / MHZ); in _gk20a_pllg_program_mnp()
366 int ret = gk20a_pllg_slide(clk, n_lo); in _gk20a_pllg_program_mnp()
391 _gk20a_pllg_disable(clk); in _gk20a_pllg_program_mnp()
394 clk->m, clk->n, clk->pl); in _gk20a_pllg_program_mnp()
396 n_lo = DIV_ROUND_UP(clk->m * clk->params->min_vco, in _gk20a_pllg_program_mnp()
397 clk->parent_rate / MHZ); in _gk20a_pllg_program_mnp()
398 val = clk->m << GPCPLL_COEFF_M_SHIFT; in _gk20a_pllg_program_mnp()
399 val |= (allow_slide ? n_lo : clk->n) << GPCPLL_COEFF_N_SHIFT; in _gk20a_pllg_program_mnp()
400 val |= clk->pl << GPCPLL_COEFF_P_SHIFT; in _gk20a_pllg_program_mnp()
403 _gk20a_pllg_enable(clk); in _gk20a_pllg_program_mnp()
427 return allow_slide ? gk20a_pllg_slide(clk, clk->n) : 0; in _gk20a_pllg_program_mnp()
431 gk20a_pllg_program_mnp(struct gk20a_clk *clk) in gk20a_pllg_program_mnp() argument
435 err = _gk20a_pllg_program_mnp(clk, true); in gk20a_pllg_program_mnp()
437 err = _gk20a_pllg_program_mnp(clk, false); in gk20a_pllg_program_mnp()
443 gk20a_pllg_disable(struct gk20a_clk *clk) in gk20a_pllg_disable() argument
445 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_disable()
455 n_lo = DIV_ROUND_UP(m * clk->params->min_vco, in gk20a_pllg_disable()
456 clk->parent_rate / MHZ); in gk20a_pllg_disable()
457 gk20a_pllg_slide(clk, n_lo); in gk20a_pllg_disable()
463 _gk20a_pllg_disable(clk); in gk20a_pllg_disable()
565 struct gk20a_clk *clk = gk20a_clk(base); in gk20a_clk_read() local
566 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_clk_read()
573 gk20a_pllg_read_mnp(clk); in gk20a_clk_read()
574 return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV; in gk20a_clk_read()
584 struct gk20a_clk *clk = gk20a_clk(base); in gk20a_clk_calc() local
586 return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] * in gk20a_clk_calc()
593 struct gk20a_clk *clk = gk20a_clk(base); in gk20a_clk_prog() local
595 return gk20a_pllg_program_mnp(clk); in gk20a_clk_prog()
606 struct gk20a_clk *clk = gk20a_clk(base); in gk20a_clk_fini() local
607 gk20a_pllg_disable(clk); in gk20a_clk_fini()
613 struct gk20a_clk *clk = gk20a_clk(base); in gk20a_clk_init() local
614 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_clk_init()
620 ret = gk20a_clk_prog(&clk->base); in gk20a_clk_init()
650 struct gk20a_clk *clk; in gk20a_clk_new() local
653 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) in gk20a_clk_new()
655 *pclk = &clk->base; in gk20a_clk_new()
663 clk->params = &gk20a_pllg_params; in gk20a_clk_new()
664 clk->parent_rate = clk_get_rate(tdev->clk); in gk20a_clk_new()
666 ret = nvkm_clk_ctor(&gk20a_clk, device, index, true, &clk->base); in gk20a_clk_new()
667 nvkm_info(&clk->base.subdev, "parent clock rate: %d Mhz\n", in gk20a_clk_new()
668 clk->parent_rate / MHZ); in gk20a_clk_new()