43 read_vco(struct gt215_clk *clk, int idx)  in read_vco()  argument
46 	u32 sctl = nvkm_rd32(device, 0x4120 + (idx * 4));  in read_vco()
61 read_clk(struct gt215_clk *clk, int idx, bool ignore_en)  in read_clk()  argument
67 	if (idx >= 0x40) {  in read_clk()
76 	sctl = nvkm_rd32(device, 0x4120 + (idx * 4));  in read_clk()
99 		sclk = read_vco(clk, idx);  in read_clk()
108 read_pll(struct gt215_clk *clk, int idx, u32 pll)  in read_pll()  argument
127 			sclk = read_clk(clk, 0x00 + idx, false);  in read_pll()
130 		sclk = read_clk(clk, 0x10 + idx, false);  in read_pll()
184 gt215_clk_info(struct nvkm_clk *base, int idx, u32 khz,  in gt215_clk_info()  argument
204 		sclk = read_vco(clk, idx);  in gt215_clk_info()
232 gt215_pll_info(struct nvkm_clk *base, int idx, u32 pll, u32 khz,  in gt215_pll_info()  argument
245 	ret = gt215_clk_info(&clk->base, idx, khz, info);  in gt215_pll_info()
256 	ret = gt215_clk_info(&clk->base, idx - 0x10, limits.refclk, info);  in gt215_pll_info()
272 	 int idx, u32 pll, int dom)  in calc_clk()  argument
274 	int ret = gt215_pll_info(&clk->base, idx, pll, cstate->domain[dom],  in calc_clk()
360 prog_pll(struct gt215_clk *clk, int idx, u32 pll, int dom)  in prog_pll()  argument
364 	const u32 src0 = 0x004120 + (idx * 4);  in prog_pll()
365 	const u32 src1 = 0x004160 + (idx * 4);  in prog_pll()
404 prog_clk(struct gt215_clk *clk, int idx, int dom)  in prog_clk()  argument
408 	nvkm_mask(device, 0x004120 + (idx * 4), 0x003f3141, 0x00000101 | info->clk);  in prog_clk()