40 read_pll_1(struct nv40_clk *clk, u32 reg)  in read_pll_1()  argument
42 	struct nvkm_device *device = clk->base.subdev.device;  in read_pll_1()
56 read_pll_2(struct nv40_clk *clk, u32 reg)  in read_pll_2()  argument
58 	struct nvkm_device *device = clk->base.subdev.device;  in read_pll_2()
82 read_clk(struct nv40_clk *clk, u32 src)  in read_clk()  argument
86 		return read_pll_2(clk, 0x004000);  in read_clk()
88 		return read_pll_1(clk, 0x004008);  in read_clk()
99 	struct nv40_clk *clk = nv40_clk(base);  in nv40_clk_read()  local
100 	struct nvkm_subdev *subdev = &clk->base.subdev;  in nv40_clk_read()
110 		return read_clk(clk, (mast & 0x00000003) >> 0);  in nv40_clk_read()
112 		return read_clk(clk, (mast & 0x00000030) >> 4);  in nv40_clk_read()
114 		return read_pll_2(clk, 0x4020);  in nv40_clk_read()
124 nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz,  in nv40_clk_calc_pll()  argument
127 	struct nvkm_subdev *subdev = &clk->base.subdev;  in nv40_clk_calc_pll()
148 	struct nv40_clk *clk = nv40_clk(base);  in nv40_clk_calc()  local
155 	ret = nv40_clk_calc_pll(clk, 0x004000, gclk,  in nv40_clk_calc()
161 		clk->npll_ctrl = 0x80000100 | (log2P << 16);  in nv40_clk_calc()
162 		clk->npll_coef = (N1 << 8) | M1;  in nv40_clk_calc()
164 		clk->npll_ctrl = 0xc0000000 | (log2P << 16);  in nv40_clk_calc()
165 		clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;  in nv40_clk_calc()
170 		ret = nv40_clk_calc_pll(clk, 0x004008, sclk,  in nv40_clk_calc()
175 		clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;  in nv40_clk_calc()
176 		clk->ctrl = 0x00000223;  in nv40_clk_calc()
178 		clk->spll = 0x00000000;  in nv40_clk_calc()
179 		clk->ctrl = 0x00000333;  in nv40_clk_calc()
188 	struct nv40_clk *clk = nv40_clk(base);  in nv40_clk_prog()  local
189 	struct nvkm_device *device = clk->base.subdev.device;  in nv40_clk_prog()
191 	nvkm_wr32(device, 0x004004, clk->npll_coef);  in nv40_clk_prog()
192 	nvkm_mask(device, 0x004000, 0xc0070100, clk->npll_ctrl);  in nv40_clk_prog()
193 	nvkm_mask(device, 0x004008, 0xc007ffff, clk->spll);  in nv40_clk_prog()
195 	nvkm_mask(device, 0x00c040, 0x00000333, clk->ctrl);  in nv40_clk_prog()
223 	struct nv40_clk *clk;  in nv40_clk_new()  local
225 	if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL)))  in nv40_clk_new()
227 	clk->base.pll_calc = nv04_clk_pll_calc;  in nv40_clk_new()
228 	clk->base.pll_prog = nv04_clk_pll_prog;  in nv40_clk_new()
229 	*pclk = &clk->base;  in nv40_clk_new()
231 	return nvkm_clk_ctor(&nv40_clk, device, index, true, &clk->base);  in nv40_clk_new()