32 read_div(struct nv50_clk *clk)  in read_div()  argument
34 	struct nvkm_device *device = clk->base.subdev.device;  in read_div()
52 read_pll_src(struct nv50_clk *clk, u32 base)  in read_pll_src()  argument
54 	struct nvkm_subdev *subdev = &clk->base.subdev;  in read_pll_src()
56 	u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal);  in read_pll_src()
103 		case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal);  in read_pll_src()
104 		case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href);  in read_pll_src()
125 read_pll_ref(struct nv50_clk *clk, u32 base)  in read_pll_ref()  argument
127 	struct nvkm_subdev *subdev = &clk->base.subdev;  in read_pll_ref()
145 		return nvkm_clk_read(&clk->base, nv_clk_src_crystal);  in read_pll_ref()
152 		return nvkm_clk_read(&clk->base, nv_clk_src_href);  in read_pll_ref()
154 	return read_pll_src(clk, base);  in read_pll_ref()
158 read_pll(struct nv50_clk *clk, u32 base)  in read_pll()  argument
160 	struct nvkm_device *device = clk->base.subdev.device;  in read_pll()
164 	u32 ref = read_pll_ref(clk, base);  in read_pll()
171 			return nvkm_clk_read(&clk->base, nv_clk_src_dom6);  in read_pll()
194 	struct nv50_clk *clk = nv50_clk(base);  in nv50_clk_read()  local
195 	struct nvkm_subdev *subdev = &clk->base.subdev;  in nv50_clk_read()
206 		return div_u64((u64)nvkm_clk_read(&clk->base, nv_clk_src_href) * 27778, 10000);  in nv50_clk_read()
208 		return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3;  in nv50_clk_read()
210 		return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3 / 2;  in nv50_clk_read()
213 		case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);  in nv50_clk_read()
216 		case 0x30000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk);  in nv50_clk_read()
223 		case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;  in nv50_clk_read()
224 		case 0x00000001: return nvkm_clk_read(&clk->base, nv_clk_src_dom6);  in nv50_clk_read()
225 		case 0x00000002: return read_pll(clk, 0x004020) >> P;  in nv50_clk_read()
226 		case 0x00000003: return read_pll(clk, 0x004028) >> P;  in nv50_clk_read()
234 				return nvkm_clk_read(&clk->base, nv_clk_src_host) >> P;  in nv50_clk_read()
235 			return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;  in nv50_clk_read()
237 		case 0x00000020: return read_pll(clk, 0x004028) >> P;  in nv50_clk_read()
238 		case 0x00000030: return read_pll(clk, 0x004020) >> P;  in nv50_clk_read()
246 				return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;  in nv50_clk_read()
249 				return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P;  in nv50_clk_read()
252 			return read_pll(clk, 0x004008) >> P;  in nv50_clk_read()
256 		P = (read_div(clk) & 0x00000700) >> 8;  in nv50_clk_read()
267 					return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;  in nv50_clk_read()
268 				return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;  in nv50_clk_read()
273 					return read_pll(clk, 0x004028) >> P;  in nv50_clk_read()
274 				return read_pll(clk, 0x004030) >> P;  in nv50_clk_read()
276 				return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;  in nv50_clk_read()
282 				return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;  in nv50_clk_read()
286 				return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2) >> P;  in nv50_clk_read()
288 				return nvkm_clk_read(&clk->base, nv_clk_src_mem) >> P;  in nv50_clk_read()
297 			return read_pll(clk, 0x00e810) >> 2;  in nv50_clk_read()
304 			P = (read_div(clk) & 0x00000007) >> 0;  in nv50_clk_read()
306 			case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);  in nv50_clk_read()
308 			case 0x08000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk);  in nv50_clk_read()
310 				return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3) >> P;  in nv50_clk_read()
325 calc_pll(struct nv50_clk *clk, u32 reg, u32 idx, int *N, int *M, int *P)  in calc_pll()  argument
327 	struct nvkm_subdev *subdev = &clk->base.subdev;  in calc_pll()
336 	pll.refclk = read_pll_ref(clk, reg);  in calc_pll()
370 	struct nv50_clk *clk = nv50_clk(base);  in nv50_clk_calc()  local
371 	struct nv50_clk_hwsq *hwsq = &clk->hwsq;  in nv50_clk_calc()
372 	struct nvkm_subdev *subdev = &clk->base.subdev;  in nv50_clk_calc()
403 			out = read_pll(clk, 0x004030);  in nv50_clk_calc()
405 			out = nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2);  in nv50_clk_calc()
426 		if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_href))) {  in nv50_clk_calc()
429 		if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_hclk))) {  in nv50_clk_calc()
432 			freq = nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3;  in nv50_clk_calc()
459 	freq = calc_pll(clk, 0x4028, core, &N, &M, &P1);  in nv50_clk_calc()
477 		freq = calc_pll(clk, 0x4020, shader, &N, &M, &P1);  in nv50_clk_calc()
497 	struct nv50_clk *clk = nv50_clk(base);  in nv50_clk_prog()  local
498 	return clk_exec(&clk->hwsq, true);  in nv50_clk_prog()
504 	struct nv50_clk *clk = nv50_clk(base);  in nv50_clk_tidy()  local
505 	clk_exec(&clk->hwsq, false);  in nv50_clk_tidy()
512 	struct nv50_clk *clk;  in nv50_clk_new_()  local
515 	if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL)))  in nv50_clk_new_()
517 	ret = nvkm_clk_ctor(func, device, index, allow_reclock, &clk->base);  in nv50_clk_new_()
518 	*pclk = &clk->base;  in nv50_clk_new_()
522 	clk->hwsq.r_fifo = hwsq_reg(0x002504);  in nv50_clk_new_()
523 	clk->hwsq.r_spll[0] = hwsq_reg(0x004020);  in nv50_clk_new_()
524 	clk->hwsq.r_spll[1] = hwsq_reg(0x004024);  in nv50_clk_new_()
525 	clk->hwsq.r_nvpll[0] = hwsq_reg(0x004028);  in nv50_clk_new_()
526 	clk->hwsq.r_nvpll[1] = hwsq_reg(0x00402c);  in nv50_clk_new_()
531 		clk->hwsq.r_divs = hwsq_reg(0x004800);  in nv50_clk_new_()
534 		clk->hwsq.r_divs = hwsq_reg(0x004700);  in nv50_clk_new_()
537 	clk->hwsq.r_mast = hwsq_reg(0x00c040);  in nv50_clk_new_()