166 	case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET):  in cik_get_allowed_info_register()
3742 	WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);  in cik_gpu_init()
5225 		RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));  in cik_print_gpu_status_regs()
5279 	tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);  in cik_gpu_check_soft_reset()
5367 		tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);  in cik_gpu_soft_reset()
5369 		WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in cik_gpu_soft_reset()
5570 	tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);  in cik_gpu_pci_config_reset()
5572 	WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in cik_gpu_pci_config_reset()
5941 		WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0);  in cik_pcie_gart_enable()
5942 		WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0);  in cik_pcie_gart_enable()
6602 		WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);  in cik_enable_sdma_mgcg()
6605 		orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);  in cik_enable_sdma_mgcg()
6608 			WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);  in cik_enable_sdma_mgcg()
6623 		orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);  in cik_enable_sdma_mgls()
6626 			WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);  in cik_enable_sdma_mgls()
6633 		orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);  in cik_enable_sdma_mgls()
6636 			WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);  in cik_enable_sdma_mgls()
7308 	tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;  in cik_disable_interrupt_state()
7309 	WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in cik_disable_interrupt_state()
7492 	dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;  in cik_irq_set()
7602 	WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);  in cik_irq_set()