Lines Matching refs:RREG32
48 r = RREG32(EVERGREEN_CG_IND_DATA); in eg_cg_rreg()
70 r = RREG32(EVERGREEN_PIF_PHY0_DATA); in eg_pif_phy0_rreg()
92 r = RREG32(EVERGREEN_PIF_PHY1_DATA); in eg_pif_phy1_rreg()
1099 *val = RREG32(reg); in evergreen_get_allowed_info_register()
1151 if (RREG32(status_reg) & DCLK_STATUS) in sumo_set_uvd_clock()
1164 u32 cg_scratch = RREG32(CG_SCRATCH1); in sumo_set_uvd_clocks()
1345 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) in dce4_is_in_vblank()
1355 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1356 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1379 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) in dce4_wait_for_vblank()
1420 RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset); in evergreen_page_flip()
1436 return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & in evergreen_page_flip_pending()
1447 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >> in evergreen_get_temp()
1449 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >> in evergreen_get_temp()
1460 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> in evergreen_get_temp()
1481 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff; in sumo_get_temp()
1671 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_prepare()
1696 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_finish()
1718 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) in evergreen_hpd_sense()
1722 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) in evergreen_hpd_sense()
1726 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) in evergreen_hpd_sense()
1730 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) in evergreen_hpd_sense()
1734 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) in evergreen_hpd_sense()
1738 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) in evergreen_hpd_sense()
1764 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_hpd_set_polarity()
1772 tmp = RREG32(DC_HPD2_INT_CONTROL); in evergreen_hpd_set_polarity()
1780 tmp = RREG32(DC_HPD3_INT_CONTROL); in evergreen_hpd_set_polarity()
1788 tmp = RREG32(DC_HPD4_INT_CONTROL); in evergreen_hpd_set_polarity()
1796 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_hpd_set_polarity()
1804 tmp = RREG32(DC_HPD6_INT_CONTROL); in evergreen_hpd_set_polarity()
1967 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in evergreen_line_buffer_adjust()
2010 u32 tmp = RREG32(MC_SHARED_CHMAP); in evergreen_get_number_of_dram_channels()
2381 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks()
2390 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks()
2460 tmp = RREG32(SRBM_STATUS) & 0x1F00; in evergreen_mc_wait_for_idle()
2481 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); in evergreen_pcie_gart_tlb_flush()
2668 dig_fe = RREG32(NI_DIG_FE_CNTL + ni_dig_offsets[i]); in evergreen_is_dp_sst_stream_enabled()
2682 dig_be = RREG32(NI_DIG_BE_CNTL + ni_dig_offsets[i]); in evergreen_is_dp_sst_stream_enabled()
2689 dig_en_be = RREG32(NI_DIG_BE_EN_CNTL + in evergreen_is_dp_sst_stream_enabled()
2691 uniphy_pll = RREG32(NI_DCIO_UNIPHY0_PLL_CONTROL1 + in evergreen_is_dp_sst_stream_enabled()
2724 stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL + in evergreen_blank_dp_output()
2735 stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL + in evergreen_blank_dp_output()
2740 stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL + in evergreen_blank_dp_output()
2746 fifo_ctrl = RREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe]); in evergreen_blank_dp_output()
2759 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); in evergreen_mc_stop()
2760 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); in evergreen_mc_stop()
2767 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; in evergreen_mc_stop()
2771 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2780 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2809 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2822 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); in evergreen_mc_stop()
2836 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_stop()
2841 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); in evergreen_mc_stop()
2875 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]); in evergreen_mc_resume()
2881 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_resume()
2886 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); in evergreen_mc_resume()
2892 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_resume()
2901 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); in evergreen_mc_resume()
2910 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); in evergreen_mc_resume()
2916 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_resume()
2987 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF; in evergreen_mc_program()
3166 RREG32(GRBM_SOFT_RESET); in evergreen_cp_resume()
3169 RREG32(GRBM_SOFT_RESET); in evergreen_cp_resume()
3489 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); in evergreen_gpu_init()
3493 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG); in evergreen_gpu_init()
3495 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); in evergreen_gpu_init()
3556 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; in evergreen_gpu_init()
3577 simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; in evergreen_gpu_init()
3627 sx_debug_1 = RREG32(SX_DEBUG_1); in evergreen_gpu_init()
3632 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); in evergreen_gpu_init()
3658 sq_config = RREG32(SQ_CONFIG); in evergreen_gpu_init()
3683 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT); in evergreen_gpu_init()
3785 tmp = RREG32(HDP_MISC_CNTL); in evergreen_gpu_init()
3789 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); in evergreen_gpu_init()
3808 tmp = RREG32(FUS_MC_ARB_RAMCFG); in evergreen_mc_init()
3810 tmp = RREG32(MC_ARB_RAMCFG); in evergreen_mc_init()
3818 tmp = RREG32(MC_SHARED_CHMAP); in evergreen_mc_init()
3843 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in evergreen_mc_init()
3844 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in evergreen_mc_init()
3847 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in evergreen_mc_init()
3848 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in evergreen_mc_init()
3860 RREG32(GRBM_STATUS)); in evergreen_print_gpu_status_regs()
3862 RREG32(GRBM_STATUS_SE0)); in evergreen_print_gpu_status_regs()
3864 RREG32(GRBM_STATUS_SE1)); in evergreen_print_gpu_status_regs()
3866 RREG32(SRBM_STATUS)); in evergreen_print_gpu_status_regs()
3868 RREG32(SRBM_STATUS2)); in evergreen_print_gpu_status_regs()
3870 RREG32(CP_STALLED_STAT1)); in evergreen_print_gpu_status_regs()
3872 RREG32(CP_STALLED_STAT2)); in evergreen_print_gpu_status_regs()
3874 RREG32(CP_BUSY_STAT)); in evergreen_print_gpu_status_regs()
3876 RREG32(CP_STAT)); in evergreen_print_gpu_status_regs()
3878 RREG32(DMA_STATUS_REG)); in evergreen_print_gpu_status_regs()
3881 RREG32(DMA_STATUS_REG + 0x800)); in evergreen_print_gpu_status_regs()
3892 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) { in evergreen_is_display_hung()
3893 crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in evergreen_is_display_hung()
3901 tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in evergreen_is_display_hung()
3920 tmp = RREG32(GRBM_STATUS); in evergreen_gpu_check_soft_reset()
3936 tmp = RREG32(DMA_STATUS_REG); in evergreen_gpu_check_soft_reset()
3941 tmp = RREG32(SRBM_STATUS2); in evergreen_gpu_check_soft_reset()
3946 tmp = RREG32(SRBM_STATUS); in evergreen_gpu_check_soft_reset()
3970 tmp = RREG32(VM_L2_STATUS); in evergreen_gpu_check_soft_reset()
4001 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_soft_reset()
4061 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4065 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4071 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4075 tmp = RREG32(SRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4079 tmp = RREG32(SRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4085 tmp = RREG32(SRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4110 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_pci_config_reset()
4133 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) in evergreen_gpu_pci_config_reset()
4481 u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; in evergreen_rlc_resume()
4538 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in evergreen_get_vblank_counter()
4550 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state()
4554 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state()
4585 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4587 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4589 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4591 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4593 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4595 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4623 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in evergreen_irq_set()
4624 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in evergreen_irq_set()
4625 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in evergreen_irq_set()
4626 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in evergreen_irq_set()
4627 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in evergreen_irq_set()
4628 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in evergreen_irq_set()
4630 thermal_int = RREG32(TN_CG_THERMAL_INT_CTRL) & in evergreen_irq_set()
4633 thermal_int = RREG32(CG_THERMAL_INT) & in evergreen_irq_set()
4636 …afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4637 …afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4638 …afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4639 …afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4640 …afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4641 …afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4643 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_irq_set()
4673 dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; in evergreen_irq_set()
4825 RREG32(SRBM_STATUS); in evergreen_irq_set()
4834 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); in evergreen_irq_ack()
4835 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in evergreen_irq_ack()
4836 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); in evergreen_irq_ack()
4837 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); in evergreen_irq_ack()
4838 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); in evergreen_irq_ack()
4839 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); in evergreen_irq_ack()
4840 …rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSE… in evergreen_irq_ack()
4841 …rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSE… in evergreen_irq_ack()
4843 …rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSE… in evergreen_irq_ack()
4844 …rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSE… in evergreen_irq_ack()
4847 …rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSE… in evergreen_irq_ack()
4848 …rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSE… in evergreen_irq_ack()
4851 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); in evergreen_irq_ack()
4852 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); in evergreen_irq_ack()
4853 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); in evergreen_irq_ack()
4854 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); in evergreen_irq_ack()
4855 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); in evergreen_irq_ack()
4856 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); in evergreen_irq_ack()
4902 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_irq_ack()
4907 tmp = RREG32(DC_HPD2_INT_CONTROL); in evergreen_irq_ack()
4912 tmp = RREG32(DC_HPD3_INT_CONTROL); in evergreen_irq_ack()
4917 tmp = RREG32(DC_HPD4_INT_CONTROL); in evergreen_irq_ack()
4922 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4927 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4933 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_irq_ack()
4938 tmp = RREG32(DC_HPD2_INT_CONTROL); in evergreen_irq_ack()
4943 tmp = RREG32(DC_HPD3_INT_CONTROL); in evergreen_irq_ack()
4948 tmp = RREG32(DC_HPD4_INT_CONTROL); in evergreen_irq_ack()
4953 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4958 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4964 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); in evergreen_irq_ack()
4969 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); in evergreen_irq_ack()
4974 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); in evergreen_irq_ack()
4979 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); in evergreen_irq_ack()
4984 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); in evergreen_irq_ack()
4989 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); in evergreen_irq_ack()
5017 wptr = RREG32(IH_RB_WPTR); in evergreen_get_ih_wptr()
5028 tmp = RREG32(IH_RB_CNTL); in evergreen_get_ih_wptr()
5421 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); in evergreen_irq_process()
5430 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); in evergreen_irq_process()
5431 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS); in evergreen_irq_process()