Lines Matching refs:idx
755 unsigned idx) in evergreen_cs_track_validate_texture() argument
763 texdw[0] = radeon_get_ib_value(p, idx + 0); in evergreen_cs_track_validate_texture()
764 texdw[1] = radeon_get_ib_value(p, idx + 1); in evergreen_cs_track_validate_texture()
765 texdw[2] = radeon_get_ib_value(p, idx + 2); in evergreen_cs_track_validate_texture()
766 texdw[3] = radeon_get_ib_value(p, idx + 3); in evergreen_cs_track_validate_texture()
767 texdw[4] = radeon_get_ib_value(p, idx + 4); in evergreen_cs_track_validate_texture()
768 texdw[5] = radeon_get_ib_value(p, idx + 5); in evergreen_cs_track_validate_texture()
769 texdw[6] = radeon_get_ib_value(p, idx + 6); in evergreen_cs_track_validate_texture()
770 texdw[7] = radeon_get_ib_value(p, idx + 7); in evergreen_cs_track_validate_texture()
1049 unsigned idx, unsigned reg) in evergreen_packet0_check() argument
1058 idx, reg); in evergreen_packet0_check()
1064 reg, idx); in evergreen_packet0_check()
1074 unsigned idx; in evergreen_cs_parse_packet0() local
1077 idx = pkt->idx + 1; in evergreen_cs_parse_packet0()
1079 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { in evergreen_cs_parse_packet0()
1080 r = evergreen_packet0_check(p, pkt, idx, reg); in evergreen_cs_parse_packet0()
1094 static int evergreen_cs_handle_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) in evergreen_cs_handle_reg() argument
1149 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1152 track->db_depth_control = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1170 track->db_z_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1178 ib[idx] &= ~Z_ARRAY_MODE(0xf); in evergreen_cs_handle_reg()
1180 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1188 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1189 ib[idx] |= DB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1198 track->db_s_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1202 track->db_depth_view = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1206 track->db_depth_size = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1210 track->db_depth_slice = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1220 track->db_z_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1221 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1232 track->db_z_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1233 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1244 track->db_s_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1245 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1256 track->db_s_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1257 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1262 track->vgt_strmout_config = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1266 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1280 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in evergreen_cs_handle_reg()
1281 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1291 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in evergreen_cs_handle_reg()
1301 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1303 track->cb_target_mask = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1307 track->cb_shader_mask = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1316 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK; in evergreen_cs_handle_reg()
1325 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK; in evergreen_cs_handle_reg()
1337 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1345 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1357 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1365 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1375 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1383 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1397 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1405 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1417 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1418 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_handle_reg()
1426 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1427 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_handle_reg()
1451 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1452 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1459 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1479 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1480 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1487 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1504 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1521 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1533 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1544 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1561 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1562 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1577 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1578 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1589 track->htile_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1590 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1596 track->htile_surface = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1598 ib[idx] |= 3; in evergreen_cs_handle_reg()
1707 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1721 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1735 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1738 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in evergreen_cs_handle_reg()
1741 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in evergreen_cs_handle_reg()
1777 unsigned idx; in evergreen_packet3_check() local
1785 idx = pkt->idx + 1; in evergreen_packet3_check()
1786 idx_value = radeon_get_ib_value(p, idx); in evergreen_packet3_check()
1800 tmp = radeon_get_ib_value(p, idx + 1); in evergreen_packet3_check()
1822 ib[idx + 0] = offset; in evergreen_packet3_check()
1823 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
1866 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
1868 ib[idx+0] = offset; in evergreen_packet3_check()
1869 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1901 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
1903 ib[idx+0] = offset; in evergreen_packet3_check()
1904 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1928 radeon_get_ib_value(p, idx+1) + in evergreen_packet3_check()
1929 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
1931 ib[idx+1] = offset; in evergreen_packet3_check()
1932 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1948 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
1959 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
2024 ib[idx+1] = reloc->gpu_offset; in evergreen_packet3_check()
2025 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; in evergreen_packet3_check()
2064 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
2078 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2101 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2102 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2104 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc); in evergreen_packet3_check()
2105 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2119 command = radeon_get_ib_value(p, idx+4); in evergreen_packet3_check()
2121 info = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2154 tmp = radeon_get_ib_value(p, idx) + in evergreen_packet3_check()
2155 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
2165 ib[idx] = offset; in evergreen_packet3_check()
2166 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2192 tmp = radeon_get_ib_value(p, idx+2) + in evergreen_packet3_check()
2193 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); in evergreen_packet3_check()
2203 ib[idx+2] = offset; in evergreen_packet3_check()
2204 ib[idx+3] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2218 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || in evergreen_packet3_check()
2219 radeon_get_ib_value(p, idx + 2) != 0) { in evergreen_packet3_check()
2225 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2242 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + in evergreen_packet3_check()
2243 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2245 ib[idx+1] = offset & 0xfffffff8; in evergreen_packet3_check()
2246 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2264 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2265 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2267 ib[idx+1] = offset & 0xfffffffc; in evergreen_packet3_check()
2268 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2286 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2287 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2289 ib[idx+1] = offset & 0xfffffffc; in evergreen_packet3_check()
2290 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2302 for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) { in evergreen_packet3_check()
2305 r = evergreen_cs_handle_reg(p, reg, idx); in evergreen_packet3_check()
2319 for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) { in evergreen_packet3_check()
2322 r = evergreen_cs_handle_reg(p, reg, idx); in evergreen_packet3_check()
2345 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { in evergreen_packet3_check()
2354 ib[idx+1+(i*8)+1] |= in evergreen_packet3_check()
2362 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split); in evergreen_packet3_check()
2363 ib[idx+1+(i*8)+7] |= in evergreen_packet3_check()
2374 tex_dim = ib[idx+1+(i*8)+0] & 0x7; in evergreen_packet3_check()
2375 mip_address = ib[idx+1+(i*8)+3]; in evergreen_packet3_check()
2394 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8)); in evergreen_packet3_check()
2397 ib[idx+1+(i*8)+2] += toffset; in evergreen_packet3_check()
2398 ib[idx+1+(i*8)+3] += moffset; in evergreen_packet3_check()
2409 offset = radeon_get_ib_value(p, idx+1+(i*8)+0); in evergreen_packet3_check()
2410 size = radeon_get_ib_value(p, idx+1+(i*8)+1); in evergreen_packet3_check()
2414 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; in evergreen_packet3_check()
2418 ib[idx+1+(i*8)+0] = offset64; in evergreen_packet3_check()
2419 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | in evergreen_packet3_check()
2491 offset = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2492 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_packet3_check()
2499 ib[idx+1] = offset; in evergreen_packet3_check()
2500 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2510 offset = radeon_get_ib_value(p, idx+3); in evergreen_packet3_check()
2511 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_packet3_check()
2518 ib[idx+3] = offset; in evergreen_packet3_check()
2519 ib[idx+4] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2535 offset = radeon_get_ib_value(p, idx+0); in evergreen_packet3_check()
2536 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; in evergreen_packet3_check()
2547 ib[idx+0] = offset; in evergreen_packet3_check()
2548 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2564 offset = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2565 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_packet3_check()
2572 ib[idx+1] = offset; in evergreen_packet3_check()
2573 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2576 reg = radeon_get_ib_value(p, idx+1) << 2; in evergreen_packet3_check()
2579 reg, idx + 1); in evergreen_packet3_check()
2591 offset = radeon_get_ib_value(p, idx+3); in evergreen_packet3_check()
2592 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_packet3_check()
2599 ib[idx+3] = offset; in evergreen_packet3_check()
2600 ib[idx+4] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2603 reg = radeon_get_ib_value(p, idx+3) << 2; in evergreen_packet3_check()
2606 reg, idx + 3); in evergreen_packet3_check()
2697 r = radeon_cs_packet_parse(p, &pkt, p->idx); in evergreen_cs_parse()
2703 p->idx += pkt.count + 2; in evergreen_cs_parse()
2724 } while (p->idx < p->chunk_ib->length_dw); in evergreen_cs_parse()
2751 u32 idx; in evergreen_dma_cs_parse() local
2756 if (p->idx >= ib_chunk->length_dw) { in evergreen_dma_cs_parse()
2758 p->idx, ib_chunk->length_dw); in evergreen_dma_cs_parse()
2761 idx = p->idx; in evergreen_dma_cs_parse()
2762 header = radeon_get_ib_value(p, idx); in evergreen_dma_cs_parse()
2777 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2780 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2781 p->idx += count + 7; in evergreen_dma_cs_parse()
2785 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2786 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_dma_cs_parse()
2788 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2789 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2790 p->idx += count + 3; in evergreen_dma_cs_parse()
2793 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, header); in evergreen_dma_cs_parse()
2817 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2818 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2819 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2820 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2831 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2832 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2833 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2834 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2835 p->idx += 5; in evergreen_dma_cs_parse()
2840 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
2842 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2844 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2846 dst_offset = radeon_get_ib_value(p, idx + 7); in evergreen_dma_cs_parse()
2847 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2848 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2849 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2852 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
2853 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2854 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2855 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2857 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2859 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2871 p->idx += 9; in evergreen_dma_cs_parse()
2876 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2877 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2878 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2879 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2890 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2891 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2892 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2893 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2894 p->idx += 5; in evergreen_dma_cs_parse()
2903 ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2904 ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2905 ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2906 ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2908 p->idx += 9; in evergreen_dma_cs_parse()
2918 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2919 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2920 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2921 dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32; in evergreen_dma_cs_parse()
2922 src_offset = radeon_get_ib_value(p, idx+3); in evergreen_dma_cs_parse()
2923 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in evergreen_dma_cs_parse()
2939 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2940 ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2941 ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2942 ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2943 ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2944 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2945 p->idx += 7; in evergreen_dma_cs_parse()
2949 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
2958 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2960 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2962 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
2963 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
2979 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2980 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2981 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2982 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2983 p->idx += 10; in evergreen_dma_cs_parse()
2993 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
2995 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2997 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2998 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3001 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3002 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3004 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3006 p->idx += 12; in evergreen_dma_cs_parse()
3011 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3020 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3022 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3024 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3025 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3041 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3042 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3043 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3044 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3045 p->idx += 10; in evergreen_dma_cs_parse()
3051 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3053 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3055 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3057 dst_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3058 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3059 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3060 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3063 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3064 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3065 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3066 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3068 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3070 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3082 p->idx += 9; in evergreen_dma_cs_parse()
3091 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3092 ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3093 p->idx += 13; in evergreen_dma_cs_parse()
3098 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3107 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3109 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3111 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3112 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3128 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3129 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3130 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3131 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3132 p->idx += 10; in evergreen_dma_cs_parse()
3135 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, header); in evergreen_dma_cs_parse()
3145 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3146 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; in evergreen_dma_cs_parse()
3152 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3153 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; in evergreen_dma_cs_parse()
3154 p->idx += 4; in evergreen_dma_cs_parse()
3157 p->idx += 1; in evergreen_dma_cs_parse()
3160 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); in evergreen_dma_cs_parse()
3163 } while (p->idx < p->chunk_ib->length_dw); in evergreen_dma_cs_parse()
3299 u32 idx = pkt->idx + 1; in evergreen_vm_packet3_check() local
3300 u32 idx_value = ib[idx]; in evergreen_vm_packet3_check()
3356 reg = ib[idx + 5] * 4; in evergreen_vm_packet3_check()
3363 reg = ib[idx + 3] * 4; in evergreen_vm_packet3_check()
3384 command = ib[idx + 4]; in evergreen_vm_packet3_check()
3385 info = ib[idx + 1]; in evergreen_vm_packet3_check()
3422 start_reg = ib[idx + 2]; in evergreen_vm_packet3_check()
3450 u32 idx = 0; in evergreen_ib_parse() local
3454 pkt.idx = idx; in evergreen_ib_parse()
3455 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]); in evergreen_ib_parse()
3456 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]); in evergreen_ib_parse()
3464 idx += 1; in evergreen_ib_parse()
3467 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]); in evergreen_ib_parse()
3469 idx += pkt.count + 2; in evergreen_ib_parse()
3478 } while (idx < ib->length_dw); in evergreen_ib_parse()
3494 u32 idx = 0; in evergreen_dma_ib_parse() local
3498 header = ib->ptr[idx]; in evergreen_dma_ib_parse()
3508 idx += count + 7; in evergreen_dma_ib_parse()
3512 idx += count + 3; in evergreen_dma_ib_parse()
3515 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, ib->ptr[idx]); in evergreen_dma_ib_parse()
3523 idx += 5; in evergreen_dma_ib_parse()
3527 idx += 9; in evergreen_dma_ib_parse()
3531 idx += 5; in evergreen_dma_ib_parse()
3535 idx += 9; in evergreen_dma_ib_parse()
3539 idx += 7; in evergreen_dma_ib_parse()
3543 idx += 10; in evergreen_dma_ib_parse()
3547 idx += 12; in evergreen_dma_ib_parse()
3551 idx += 10; in evergreen_dma_ib_parse()
3555 idx += 9; in evergreen_dma_ib_parse()
3559 idx += 13; in evergreen_dma_ib_parse()
3563 idx += 10; in evergreen_dma_ib_parse()
3566 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, ib->ptr[idx]); in evergreen_dma_ib_parse()
3571 idx += 4; in evergreen_dma_ib_parse()
3574 idx += 1; in evergreen_dma_ib_parse()
3577 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); in evergreen_dma_ib_parse()
3580 } while (idx < ib->length_dw); in evergreen_dma_ib_parse()