49 	r = RREG32(TN_SMC_IND_DATA_0);  in tn_smc_rreg()
668 	mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;  in ni_mc_load_microcode()
669 	running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;  in ni_mc_load_microcode()
673 			blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);  in ni_mc_load_microcode()
698 			if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)  in ni_mc_load_microcode()
878 		*val = RREG32(reg);  in cayman_get_allowed_info_register()
1024 	mc_shared_chmap = RREG32(MC_SHARED_CHMAP);  in cayman_gpu_init()
1025 	mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);  in cayman_gpu_init()
1102 		rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;  in cayman_gpu_init()
1122 		simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;  in cayman_gpu_init()
1170 	cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);  in cayman_gpu_init()
1178 	sx_debug_1 = RREG32(SX_DEBUG_1);  in cayman_gpu_init()
1182 	smx_dc_ctl0 = RREG32(SMX_DC_CTL0);  in cayman_gpu_init()
1244 	tmp = RREG32(HDP_MISC_CNTL);  in cayman_gpu_init()
1248 	hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);  in cayman_gpu_init()
1367 		rdev->vm_manager.saved_table_addr[i] = RREG32(  in cayman_pcie_gart_disable()
1399 	u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;  in cayman_cp_int_cntl_setup()
1489 			rptr = RREG32(CP_RB0_RPTR);  in cayman_gfx_get_rptr()
1491 			rptr = RREG32(CP_RB1_RPTR);  in cayman_gfx_get_rptr()
1493 			rptr = RREG32(CP_RB2_RPTR);  in cayman_gfx_get_rptr()
1505 		wptr = RREG32(CP_RB0_WPTR);  in cayman_gfx_get_wptr()
1507 		wptr = RREG32(CP_RB1_WPTR);  in cayman_gfx_get_wptr()
1509 		wptr = RREG32(CP_RB2_WPTR);  in cayman_gfx_get_wptr()
1519 		(void)RREG32(CP_RB0_WPTR);  in cayman_gfx_set_wptr()
1522 		(void)RREG32(CP_RB1_WPTR);  in cayman_gfx_set_wptr()
1525 		(void)RREG32(CP_RB2_WPTR);  in cayman_gfx_set_wptr()
1677 	RREG32(GRBM_SOFT_RESET);  in cayman_cp_resume()
1680 	RREG32(GRBM_SOFT_RESET);  in cayman_cp_resume()
1758 	tmp = RREG32(GRBM_STATUS);  in cayman_gpu_check_soft_reset()
1775 	tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);  in cayman_gpu_check_soft_reset()
1780 	tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);  in cayman_gpu_check_soft_reset()
1785 	tmp = RREG32(SRBM_STATUS2);  in cayman_gpu_check_soft_reset()
1793 	tmp = RREG32(SRBM_STATUS);  in cayman_gpu_check_soft_reset()
1817 	tmp = RREG32(VM_L2_STATUS);  in cayman_gpu_check_soft_reset()
1843 		 RREG32(0x14F8));  in cayman_gpu_soft_reset()
1845 		 RREG32(0x14D8));  in cayman_gpu_soft_reset()
1847 		 RREG32(0x14FC));  in cayman_gpu_soft_reset()
1849 		 RREG32(0x14DC));  in cayman_gpu_soft_reset()
1856 		tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);  in cayman_gpu_soft_reset()
1863 		tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);  in cayman_gpu_soft_reset()
1926 		tmp = RREG32(GRBM_SOFT_RESET);  in cayman_gpu_soft_reset()
1930 		tmp = RREG32(GRBM_SOFT_RESET);  in cayman_gpu_soft_reset()
1936 		tmp = RREG32(GRBM_SOFT_RESET);  in cayman_gpu_soft_reset()
1940 		tmp = RREG32(SRBM_SOFT_RESET);  in cayman_gpu_soft_reset()
1944 		tmp = RREG32(SRBM_SOFT_RESET);  in cayman_gpu_soft_reset()
1950 		tmp = RREG32(SRBM_SOFT_RESET);  in cayman_gpu_soft_reset()
2422 		u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);  in cayman_vm_init()
2643 		if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)  in tn_set_vce_clocks()
2653 		if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)  in tn_set_vce_clocks()