638 	u32 idx_value;  in r300_packet0_check()  local
642 	idx_value = radeon_get_ib_value(p, idx);  in r300_packet0_check()
674 		track->cb[i].offset = idx_value;  in r300_packet0_check()
676 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
687 		track->zb.offset = idx_value;  in r300_packet0_check()
689 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
717 			ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */  in r300_packet0_check()
718 				  ((idx_value & ~31) + (u32)reloc->gpu_offset);  in r300_packet0_check()
727 			tmp = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
737 		track->vap_vf_cntl = idx_value;  in r300_packet0_check()
741 		track->vtx_size = idx_value & 0x7F;  in r300_packet0_check()
745 		track->max_indx = idx_value & 0x00FFFFFFUL;  in r300_packet0_check()
751 		track->vap_alt_nverts = idx_value & 0xFFFFFF;  in r300_packet0_check()
755 		track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;  in r300_packet0_check()
764 		if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */  in r300_packet0_check()
769 		track->num_cb = ((idx_value >> 5) & 0x3) + 1;  in r300_packet0_check()
796 			tmp = idx_value & ~(0x7 << 16);  in r300_packet0_check()
801 		track->cb[i].pitch = idx_value & 0x3FFE;  in r300_packet0_check()
802 		switch (((idx_value >> 21) & 0xF)) {  in r300_packet0_check()
817 					  ((idx_value >> 21) & 0xF));  in r300_packet0_check()
832 				  ((idx_value >> 21) & 0xF));  in r300_packet0_check()
839 		if (idx_value & 2) {  in r300_packet0_check()
848 		switch ((idx_value & 0xF)) {  in r300_packet0_check()
858 				  (idx_value & 0xF));  in r300_packet0_check()
881 			tmp = idx_value & ~(0x7 << 16);  in r300_packet0_check()
885 		track->zb.pitch = idx_value & 0x3FFC;  in r300_packet0_check()
893 			enabled = !!(idx_value & (1 << i));  in r300_packet0_check()
916 		tmp = (idx_value >> 25) & 0x3;  in r300_packet0_check()
918 		switch ((idx_value & 0x1F)) {  in r300_packet0_check()
967 					  (idx_value & 0x1F));  in r300_packet0_check()
979 				  (idx_value & 0x1F));  in r300_packet0_check()
1002 		tmp = idx_value & 0x7;  in r300_packet0_check()
1006 		tmp = (idx_value >> 3) & 0x7;  in r300_packet0_check()
1030 		tmp = idx_value & 0x3FFF;  in r300_packet0_check()
1033 			tmp = ((idx_value >> 15) & 1) << 11;  in r300_packet0_check()
1035 			tmp = ((idx_value >> 16) & 1) << 11;  in r300_packet0_check()
1039 			if (idx_value & (1 << 14)) {  in r300_packet0_check()
1044 		} else if (idx_value & (1 << 14)) {  in r300_packet0_check()
1068 		tmp = idx_value & 0x7FF;  in r300_packet0_check()
1070 		tmp = (idx_value >> 11) & 0x7FF;  in r300_packet0_check()
1072 		tmp = (idx_value >> 26) & 0xF;  in r300_packet0_check()
1074 		tmp = idx_value & (1 << 31);  in r300_packet0_check()
1076 		tmp = (idx_value >> 22) & 0xF;  in r300_packet0_check()
1088 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1092 		track->color_channel_mask = idx_value;  in r300_packet0_check()
1100 			if (idx_value & 0x1)  in r300_packet0_check()
1101 				ib[idx] = idx_value & ~1;  in r300_packet0_check()
1106 		track->zb_cb_clear = !!(idx_value & (1 << 5));  in r300_packet0_check()
1110 			if (idx_value & (R300_HIZ_ENABLE |  in r300_packet0_check()
1119 		track->blend_read_enable = !!(idx_value & (1 << 2));  in r300_packet0_check()
1131 		track->aa.offset = idx_value;  in r300_packet0_check()
1133 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1136 		track->aa.pitch = idx_value & 0x3FFE;  in r300_packet0_check()
1140 		track->aaresolve = idx_value & 0x1;  in r300_packet0_check()
1147 		if (idx_value && (p->rdev->hyperz_filp != p->filp))  in r300_packet0_check()
1151 		if (idx_value && (p->rdev->hyperz_filp != p->filp))  in r300_packet0_check()
1169 	       reg, idx, idx_value);  in r300_packet0_check()