Lines Matching refs:RREG32
121 r = RREG32(R600_RCU_DATA); in r600_rcu_rreg()
143 r = RREG32(R600_UVD_CTX_DATA); in r600_uvd_ctx_rreg()
177 *val = RREG32(reg); in r600_get_allowed_info_register()
346 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> in rv6xx_get_temp()
791 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) in r600_gui_idle()
805 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
809 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
813 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
817 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
822 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
826 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
835 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) in r600_hpd_sense()
839 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) in r600_hpd_sense()
843 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) in r600_hpd_sense()
862 tmp = RREG32(DC_HPD1_INT_CONTROL); in r600_hpd_set_polarity()
870 tmp = RREG32(DC_HPD2_INT_CONTROL); in r600_hpd_set_polarity()
878 tmp = RREG32(DC_HPD3_INT_CONTROL); in r600_hpd_set_polarity()
886 tmp = RREG32(DC_HPD4_INT_CONTROL); in r600_hpd_set_polarity()
894 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_hpd_set_polarity()
903 tmp = RREG32(DC_HPD6_INT_CONTROL); in r600_hpd_set_polarity()
916 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); in r600_hpd_set_polarity()
924 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); in r600_hpd_set_polarity()
932 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); in r600_hpd_set_polarity()
1092 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); in r600_pcie_gart_tlb_flush()
1262 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; in r600_mc_wait_for_idle()
1277 r = RREG32(R_0028FC_MC_DATA); in rs780_mc_rreg()
1417 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; in r600_vram_gtt_location()
1435 tmp = RREG32(RAMCFG); in r600_mc_init()
1443 tmp = RREG32(CHMAP); in r600_mc_init()
1464 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1465 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1549 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); in r600_set_bios_scratch_engine_hung()
1562 RREG32(R_008010_GRBM_STATUS)); in r600_print_gpu_status_regs()
1564 RREG32(R_008014_GRBM_STATUS2)); in r600_print_gpu_status_regs()
1566 RREG32(R_000E50_SRBM_STATUS)); in r600_print_gpu_status_regs()
1568 RREG32(CP_STALLED_STAT1)); in r600_print_gpu_status_regs()
1570 RREG32(CP_STALLED_STAT2)); in r600_print_gpu_status_regs()
1572 RREG32(CP_BUSY_STAT)); in r600_print_gpu_status_regs()
1574 RREG32(CP_STAT)); in r600_print_gpu_status_regs()
1576 RREG32(DMA_STATUS_REG)); in r600_print_gpu_status_regs()
1586 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { in r600_is_display_hung()
1587 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()
1595 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()
1614 tmp = RREG32(R_008010_GRBM_STATUS); in r600_gpu_check_soft_reset()
1639 tmp = RREG32(DMA_STATUS_REG); in r600_gpu_check_soft_reset()
1644 tmp = RREG32(R_000E50_SRBM_STATUS); in r600_gpu_check_soft_reset()
1701 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_soft_reset()
1777 tmp = RREG32(R_008020_GRBM_SOFT_RESET); in r600_gpu_soft_reset()
1781 tmp = RREG32(R_008020_GRBM_SOFT_RESET); in r600_gpu_soft_reset()
1787 tmp = RREG32(R_008020_GRBM_SOFT_RESET); in r600_gpu_soft_reset()
1791 tmp = RREG32(SRBM_SOFT_RESET); in r600_gpu_soft_reset()
1795 tmp = RREG32(SRBM_SOFT_RESET); in r600_gpu_soft_reset()
1801 tmp = RREG32(SRBM_SOFT_RESET); in r600_gpu_soft_reset()
1832 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_pci_config_reset()
1850 tmp = RREG32(BUS_CNTL); in r600_gpu_pci_config_reset()
1854 tmp = RREG32(BIF_SCRATCH0); in r600_gpu_pci_config_reset()
1868 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) in r600_gpu_pci_config_reset()
2075 ramcfg = RREG32(RAMCFG); in r600_gpu_init()
2107 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; in r600_gpu_init()
2112 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; in r600_gpu_init()
2147 tmp = RREG32(SX_DEBUG_1); in r600_gpu_init()
2172 tmp = RREG32(SQ_MS_FIFO_SIZES); in r600_gpu_init()
2191 sq_config = RREG32(SQ_CONFIG); in r600_gpu_init()
2365 tmp = RREG32(HDP_HOST_PATH_CNTL); in r600_gpu_init()
2368 tmp = RREG32(ARB_POP); in r600_gpu_init()
2390 (void)RREG32(PCIE_PORT_INDEX); in r600_pciep_rreg()
2391 r = RREG32(PCIE_PORT_DATA); in r600_pciep_rreg()
2402 (void)RREG32(PCIE_PORT_INDEX); in r600_pciep_wreg()
2404 (void)RREG32(PCIE_PORT_DATA); in r600_pciep_wreg()
2619 rptr = RREG32(R600_CP_RB_RPTR); in r600_gfx_get_rptr()
2629 wptr = RREG32(R600_CP_RB_WPTR); in r600_gfx_get_wptr()
2638 (void)RREG32(R600_CP_RB_WPTR); in r600_gfx_set_wptr()
2659 RREG32(GRBM_SOFT_RESET); in r600_cp_load_microcode()
2722 RREG32(GRBM_SOFT_RESET); in r600_cp_resume()
2844 tmp = RREG32(scratch); in r600_ring_test()
3144 temp = RREG32(CONFIG_CNTL); in r600_vga_set_state()
3390 tmp = RREG32(scratch); in r600_ib_test()
3491 RREG32(SRBM_SOFT_RESET); in r600_rlc_stop()
3494 RREG32(SRBM_SOFT_RESET); in r600_rlc_stop()
3546 u32 ih_cntl = RREG32(IH_CNTL); in r600_enable_interrupts()
3547 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_enable_interrupts()
3558 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_disable_interrupts()
3559 u32 ih_cntl = RREG32(IH_CNTL); in r600_disable_interrupts()
3577 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_disable_interrupt_state()
3586 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3588 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3590 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3592 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3595 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3597 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3599 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3601 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3604 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3606 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3612 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_disable_interrupt_state()
3614 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_disable_interrupt_state()
3616 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_disable_interrupt_state()
3618 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3620 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3652 interrupt_cntl = RREG32(INTERRUPT_CNTL); in r600_irq_init()
3738 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3739 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3740 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3741 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3743 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3744 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3745 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; in r600_irq_set()
3746 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; in r600_irq_set()
3748 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_irq_set()
3749 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_irq_set()
3752 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3753 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3754 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3755 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_irq_set()
3756 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_irq_set()
3759 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_irq_set()
3762 thermal_int = RREG32(CG_THERMAL_INT) & in r600_irq_set()
3765 thermal_int = RREG32(RV770_CG_THERMAL_INT) & in r600_irq_set()
3861 RREG32(R_000E50_SRBM_STATUS); in r600_irq_set()
3871 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); in r600_irq_ack()
3872 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3873 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); in r600_irq_ack()
3875 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); in r600_irq_ack()
3876 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); in r600_irq_ack()
3878 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3879 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); in r600_irq_ack()
3882 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); in r600_irq_ack()
3883 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3885 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3886 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); in r600_irq_ack()
3888 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3889 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3905 tmp = RREG32(DC_HPD1_INT_CONTROL); in r600_irq_ack()
3909 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); in r600_irq_ack()
3916 tmp = RREG32(DC_HPD2_INT_CONTROL); in r600_irq_ack()
3920 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); in r600_irq_ack()
3927 tmp = RREG32(DC_HPD3_INT_CONTROL); in r600_irq_ack()
3931 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); in r600_irq_ack()
3937 tmp = RREG32(DC_HPD4_INT_CONTROL); in r600_irq_ack()
3943 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_irq_ack()
3948 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_irq_ack()
3953 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); in r600_irq_ack()
3958 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); in r600_irq_ack()
3964 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); in r600_irq_ack()
3970 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); in r600_irq_ack()
3974 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); in r600_irq_ack()
3998 wptr = RREG32(IH_RB_WPTR); in r600_get_ih_wptr()
4009 tmp = RREG32(IH_RB_CNTL); in r600_get_ih_wptr()
4061 RREG32(IH_RB_WPTR); in r600_irq_process()
4506 link_cntl2 = RREG32(0x4088); in r600_pcie_gen2_enable()
4520 tmp = RREG32(0x541c); in r600_pcie_gen2_enable()
4570 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | in r600_get_gpu_clock_counter()
4571 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); in r600_get_gpu_clock_counter()