3275 	rdev->ih.ring_obj = NULL;  in r600_init()
3427 	rdev->ih.ring_size = ring_size;  in r600_ih_ring_init()
3428 	rdev->ih.ptr_mask = rdev->ih.ring_size - 1;  in r600_ih_ring_init()
3429 	rdev->ih.rptr = 0;  in r600_ih_ring_init()
3437 	if (rdev->ih.ring_obj == NULL) {  in r600_ih_ring_alloc()
3438 		r = radeon_bo_create(rdev, rdev->ih.ring_size,  in r600_ih_ring_alloc()
3441 				     NULL, NULL, &rdev->ih.ring_obj);  in r600_ih_ring_alloc()
3446 		r = radeon_bo_reserve(rdev->ih.ring_obj, false);  in r600_ih_ring_alloc()
3449 		r = radeon_bo_pin(rdev->ih.ring_obj,  in r600_ih_ring_alloc()
3451 				  &rdev->ih.gpu_addr);  in r600_ih_ring_alloc()
3453 			radeon_bo_unreserve(rdev->ih.ring_obj);  in r600_ih_ring_alloc()
3457 		r = radeon_bo_kmap(rdev->ih.ring_obj,  in r600_ih_ring_alloc()
3458 				   (void **)&rdev->ih.ring);  in r600_ih_ring_alloc()
3459 		radeon_bo_unreserve(rdev->ih.ring_obj);  in r600_ih_ring_alloc()
3471 	if (rdev->ih.ring_obj) {  in r600_ih_ring_fini()
3472 		r = radeon_bo_reserve(rdev->ih.ring_obj, false);  in r600_ih_ring_fini()
3474 			radeon_bo_kunmap(rdev->ih.ring_obj);  in r600_ih_ring_fini()
3475 			radeon_bo_unpin(rdev->ih.ring_obj);  in r600_ih_ring_fini()
3476 			radeon_bo_unreserve(rdev->ih.ring_obj);  in r600_ih_ring_fini()
3478 		radeon_bo_unref(&rdev->ih.ring_obj);  in r600_ih_ring_fini()
3479 		rdev->ih.ring = NULL;  in r600_ih_ring_fini()
3480 		rdev->ih.ring_obj = NULL;  in r600_ih_ring_fini()
3553 	rdev->ih.enabled = true;  in r600_enable_interrupts()
3568 	rdev->ih.enabled = false;  in r600_disable_interrupts()
3569 	rdev->ih.rptr = 0;  in r600_disable_interrupts()
3651 	WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);  in r600_irq_init()
3661 	WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);  in r600_irq_init()
3662 	rb_bufsz = order_base_2(rdev->ih.ring_size / 4);  in r600_irq_init()
3730 	if (!rdev->ih.enabled) {  in r600_irq_set()
4007 			 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);  in r600_get_ih_wptr()
4008 		rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;  in r600_get_ih_wptr()
4013 	return (wptr & rdev->ih.ptr_mask);  in r600_get_ih_wptr()
4056 	if (!rdev->ih.enabled || rdev->shutdown)  in r600_irq_process()
4067 	if (atomic_xchg(&rdev->ih.lock, 1))  in r600_irq_process()
4070 	rptr = rdev->ih.rptr;  in r600_irq_process()
4082 		src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;  in r600_irq_process()
4083 		src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;  in r600_irq_process()
4275 		rptr &= rdev->ih.ptr_mask;  in r600_irq_process()
4284 	rdev->ih.rptr = rptr;  in r600_irq_process()
4285 	atomic_set(&rdev->ih.lock, 0);  in r600_irq_process()