Lines Matching refs:mc
1087 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_tlb_flush()
1088 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); in r600_pcie_gart_tlb_flush()
1161 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_enable()
1162 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in r600_pcie_gart_enable()
1173 (unsigned)(rdev->mc.gtt_size >> 20), in r600_pcie_gart_enable()
1319 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in r600_mc_program()
1322 rdev->mc.vram_start >> 12); in r600_mc_program()
1324 rdev->mc.gtt_end >> 12); in r600_mc_program()
1328 rdev->mc.gtt_start >> 12); in r600_mc_program()
1330 rdev->mc.vram_end >> 12); in r600_mc_program()
1333 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); in r600_mc_program()
1334 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); in r600_mc_program()
1337 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in r600_mc_program()
1338 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in r600_mc_program()
1340 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in r600_mc_program()
1344 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); in r600_mc_program()
1345 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); in r600_mc_program()
1346 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in r600_mc_program()
1382 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) in r600_vram_gtt_location() argument
1386 if (mc->mc_vram_size > 0xE0000000) { in r600_vram_gtt_location()
1389 mc->real_vram_size = 0xE0000000; in r600_vram_gtt_location()
1390 mc->mc_vram_size = 0xE0000000; in r600_vram_gtt_location()
1393 size_bf = mc->gtt_start; in r600_vram_gtt_location()
1394 size_af = mc->mc_mask - mc->gtt_end; in r600_vram_gtt_location()
1396 if (mc->mc_vram_size > size_bf) { in r600_vram_gtt_location()
1398 mc->real_vram_size = size_bf; in r600_vram_gtt_location()
1399 mc->mc_vram_size = size_bf; in r600_vram_gtt_location()
1401 mc->vram_start = mc->gtt_start - mc->mc_vram_size; in r600_vram_gtt_location()
1403 if (mc->mc_vram_size > size_af) { in r600_vram_gtt_location()
1405 mc->real_vram_size = size_af; in r600_vram_gtt_location()
1406 mc->mc_vram_size = size_af; in r600_vram_gtt_location()
1408 mc->vram_start = mc->gtt_end + 1; in r600_vram_gtt_location()
1410 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in r600_vram_gtt_location()
1412 mc->mc_vram_size >> 20, mc->vram_start, in r600_vram_gtt_location()
1413 mc->vram_end, mc->real_vram_size >> 20); in r600_vram_gtt_location()
1420 radeon_vram_location(rdev, &rdev->mc, base); in r600_vram_gtt_location()
1421 rdev->mc.gtt_base_align = 0; in r600_vram_gtt_location()
1422 radeon_gtt_location(rdev, mc); in r600_vram_gtt_location()
1434 rdev->mc.vram_is_ddr = true; in r600_mc_init()
1459 rdev->mc.vram_width = numchan * chansize; in r600_mc_init()
1461 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in r600_mc_init()
1462 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in r600_mc_init()
1464 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1465 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1466 rdev->mc.visible_vram_size = rdev->mc.aper_size; in r600_mc_init()
1467 r600_vram_gtt_location(rdev, &rdev->mc); in r600_mc_init()
1471 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); in r600_mc_init()
1480 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) in r600_mc_init()
1486 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { in r600_mc_init()
1488 (unsigned long long)rdev->mc.aper_base, k8_addr); in r600_mc_init()
1489 rdev->mc.aper_base = (resource_size_t)k8_addr; in r600_mc_init()
2414 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r600_cp_stop()
2772 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in r600_cp_resume()