839 	r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx);  in r600_cs_common_vline_parse()
850 	wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);  in r600_cs_common_vline_parse()
866 	if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) {  in r600_cs_common_vline_parse()
871 	if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) {  in r600_cs_common_vline_parse()
877 	r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);  in r600_cs_common_vline_parse()
881 	h_idx = p->idx - 2;  in r600_cs_common_vline_parse()
882 	p->idx += wait_reg_mem.count + 2;  in r600_cs_common_vline_parse()
883 	p->idx += p3reloc.count + 2;  in r600_cs_common_vline_parse()
920 				unsigned idx, unsigned reg)  in r600_packet0_check()  argument
929 					idx, reg);  in r600_packet0_check()
935 		       reg, idx);  in r600_packet0_check()
945 	unsigned idx;  in r600_cs_parse_packet0()  local
948 	idx = pkt->idx + 1;  in r600_cs_parse_packet0()
950 	for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {  in r600_cs_parse_packet0()
951 		r = r600_packet0_check(p, pkt, idx, reg);  in r600_cs_parse_packet0()
969 static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)  in r600_cs_check_reg()  argument
978 		dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);  in r600_cs_check_reg()
1023 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1026 		track->sq_config = radeon_get_ib_value(p, idx);  in r600_cs_check_reg()
1029 		track->db_depth_control = radeon_get_ib_value(p, idx);  in r600_cs_check_reg()
1041 			track->db_depth_info = radeon_get_ib_value(p, idx);  in r600_cs_check_reg()
1042 			ib[idx] &= C_028010_ARRAY_MODE;  in r600_cs_check_reg()
1045 				ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);  in r600_cs_check_reg()
1048 				ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);  in r600_cs_check_reg()
1052 			track->db_depth_info = radeon_get_ib_value(p, idx);  in r600_cs_check_reg()
1057 		track->db_depth_view = radeon_get_ib_value(p, idx);  in r600_cs_check_reg()
1061 		track->db_depth_size = radeon_get_ib_value(p, idx);  in r600_cs_check_reg()
1062 		track->db_depth_size_idx = idx;  in r600_cs_check_reg()
1066 		track->vgt_strmout_en = radeon_get_ib_value(p, idx);  in r600_cs_check_reg()
1070 		track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);  in r600_cs_check_reg()
1084 		track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;  in r600_cs_check_reg()
1085 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1096 		track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;  in r600_cs_check_reg()
1106 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1109 		track->cb_target_mask = radeon_get_ib_value(p, idx);  in r600_cs_check_reg()
1113 		track->cb_shader_mask = radeon_get_ib_value(p, idx);  in r600_cs_check_reg()
1116 		tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));  in r600_cs_check_reg()
1122 		tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));  in r600_cs_check_reg()
1142 			track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);  in r600_cs_check_reg()
1144 				ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);  in r600_cs_check_reg()
1147 				ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);  in r600_cs_check_reg()
1152 			track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);  in r600_cs_check_reg()
1165 		track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);  in r600_cs_check_reg()
1177 		track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);  in r600_cs_check_reg()
1178 		track->cb_color_size_idx[tmp] = idx;  in r600_cs_check_reg()
1206 			ib[idx] = track->cb_color_base_last[tmp];  in r600_cs_check_reg()
1214 			track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;  in r600_cs_check_reg()
1215 			ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1237 			ib[idx] = track->cb_color_base_last[tmp];  in r600_cs_check_reg()
1245 			track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;  in r600_cs_check_reg()
1246 			ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1261 		track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);  in r600_cs_check_reg()
1281 		track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;  in r600_cs_check_reg()
1282 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1283 		track->cb_color_base_last[tmp] = ib[idx];  in r600_cs_check_reg()
1295 		track->db_offset = radeon_get_ib_value(p, idx) << 8;  in r600_cs_check_reg()
1296 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1308 		track->htile_offset = radeon_get_ib_value(p, idx) << 8;  in r600_cs_check_reg()
1309 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1314 		track->htile_surface = radeon_get_ib_value(p, idx);  in r600_cs_check_reg()
1316 		ib[idx] |= 3;  in r600_cs_check_reg()
1378 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1387 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1390 		track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;  in r600_cs_check_reg()
1393 		dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);  in r600_cs_check_reg()
1469 static int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,  in r600_check_texture_resource()  argument
1494 	word0 = radeon_get_ib_value(p, idx + 0);  in r600_check_texture_resource()
1501 	word1 = radeon_get_ib_value(p, idx + 1);  in r600_check_texture_resource()
1502 	word2 = radeon_get_ib_value(p, idx + 2) << 8;  in r600_check_texture_resource()
1503 	word3 = radeon_get_ib_value(p, idx + 3) << 8;  in r600_check_texture_resource()
1504 	word4 = radeon_get_ib_value(p, idx + 4);  in r600_check_texture_resource()
1505 	word5 = radeon_get_ib_value(p, idx + 5);  in r600_check_texture_resource()
1610 static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)  in r600_is_safe_reg()  argument
1616 		dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);  in r600_is_safe_reg()
1622 	dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);  in r600_is_safe_reg()
1632 	unsigned idx;  in r600_packet3_check()  local
1640 	idx = pkt->idx + 1;  in r600_packet3_check()
1641 	idx_value = radeon_get_ib_value(p, idx);  in r600_packet3_check()
1655 		tmp = radeon_get_ib_value(p, idx + 1);  in r600_packet3_check()
1677 		ib[idx + 0] = offset;  in r600_packet3_check()
1678 		ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);  in r600_packet3_check()
1716 		         ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);  in r600_packet3_check()
1718 		ib[idx+0] = offset;  in r600_packet3_check()
1719 		ib[idx+1] = upper_32_bits(offset) & 0xff;  in r600_packet3_check()
1735 			dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);  in r600_packet3_check()
1767 			         (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +  in r600_packet3_check()
1768 			         ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);  in r600_packet3_check()
1770 			ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);  in r600_packet3_check()
1771 			ib[idx+2] = upper_32_bits(offset) & 0xff;  in r600_packet3_check()
1785 		command = radeon_get_ib_value(p, idx+4);  in r600_packet3_check()
1803 			tmp = radeon_get_ib_value(p, idx) +  in r600_packet3_check()
1804 				((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);  in r600_packet3_check()
1814 			ib[idx] = offset;  in r600_packet3_check()
1815 			ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);  in r600_packet3_check()
1833 			tmp = radeon_get_ib_value(p, idx+2) +  in r600_packet3_check()
1834 				((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);  in r600_packet3_check()
1844 			ib[idx+2] = offset;  in r600_packet3_check()
1845 			ib[idx+3] = upper_32_bits(offset) & 0xff;  in r600_packet3_check()
1855 		if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||  in r600_packet3_check()
1856 		    radeon_get_ib_value(p, idx + 2) != 0) {  in r600_packet3_check()
1862 			ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_packet3_check()
1879 			         (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +  in r600_packet3_check()
1880 			         ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);  in r600_packet3_check()
1882 			ib[idx+1] = offset & 0xfffffff8;  in r600_packet3_check()
1883 			ib[idx+2] = upper_32_bits(offset) & 0xff;  in r600_packet3_check()
1901 		         (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +  in r600_packet3_check()
1902 		         ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);  in r600_packet3_check()
1904 		ib[idx+1] = offset & 0xfffffffc;  in r600_packet3_check()
1905 		ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);  in r600_packet3_check()
1919 			r = r600_cs_check_reg(p, reg, idx+1+i);  in r600_packet3_check()
1935 			r = r600_cs_check_reg(p, reg, idx+1+i);  in r600_packet3_check()
1957 			switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {  in r600_packet3_check()
1968 						ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);  in r600_packet3_check()
1970 						ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);  in r600_packet3_check()
1981 				r = r600_check_texture_resource(p,  idx+(i*7)+1,  in r600_packet3_check()
1983 								base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),  in r600_packet3_check()
1984 								mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),  in r600_packet3_check()
1988 				ib[idx+1+(i*7)+2] += base_offset;  in r600_packet3_check()
1989 				ib[idx+1+(i*7)+3] += mip_offset;  in r600_packet3_check()
2000 				offset = radeon_get_ib_value(p, idx+1+(i*7)+0);  in r600_packet3_check()
2001 				size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;  in r600_packet3_check()
2006 					ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;  in r600_packet3_check()
2010 				ib[idx+1+(i*8)+0] = offset64;  in r600_packet3_check()
2011 				ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |  in r600_packet3_check()
2107 			offset = radeon_get_ib_value(p, idx+1) << 8;  in r600_packet3_check()
2119 			ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_packet3_check()
2145 			offset = radeon_get_ib_value(p, idx+1);  in r600_packet3_check()
2146 			offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;  in r600_packet3_check()
2153 			ib[idx+1] = offset;  in r600_packet3_check()
2154 			ib[idx+2] = upper_32_bits(offset) & 0xff;  in r600_packet3_check()
2164 			offset = radeon_get_ib_value(p, idx+3);  in r600_packet3_check()
2165 			offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in r600_packet3_check()
2172 			ib[idx+3] = offset;  in r600_packet3_check()
2173 			ib[idx+4] = upper_32_bits(offset) & 0xff;  in r600_packet3_check()
2189 		offset = radeon_get_ib_value(p, idx+0);  in r600_packet3_check()
2190 		offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;  in r600_packet3_check()
2201 		ib[idx+0] = offset;  in r600_packet3_check()
2202 		ib[idx+1] = upper_32_bits(offset) & 0xff;  in r600_packet3_check()
2218 			offset = radeon_get_ib_value(p, idx+1);  in r600_packet3_check()
2219 			offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;  in r600_packet3_check()
2226 			ib[idx+1] = offset;  in r600_packet3_check()
2227 			ib[idx+2] = upper_32_bits(offset) & 0xff;  in r600_packet3_check()
2230 			reg = radeon_get_ib_value(p, idx+1) << 2;  in r600_packet3_check()
2231 			if (!r600_is_safe_reg(p, reg, idx+1))  in r600_packet3_check()
2242 			offset = radeon_get_ib_value(p, idx+3);  in r600_packet3_check()
2243 			offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in r600_packet3_check()
2250 			ib[idx+3] = offset;  in r600_packet3_check()
2251 			ib[idx+4] = upper_32_bits(offset) & 0xff;  in r600_packet3_check()
2254 			reg = radeon_get_ib_value(p, idx+3) << 2;  in r600_packet3_check()
2255 			if (!r600_is_safe_reg(p, reg, idx+3))  in r600_packet3_check()
2292 		r = radeon_cs_packet_parse(p, &pkt, p->idx);  in r600_cs_parse()
2298 		p->idx += pkt.count + 2;  in r600_cs_parse()
2319 	} while (p->idx < p->chunk_ib->length_dw);  in r600_cs_parse()
2441 	unsigned idx;  in r600_dma_cs_next_reloc()  local
2449 	idx = p->dma_reloc_idx;  in r600_dma_cs_next_reloc()
2450 	if (idx >= p->nrelocs) {  in r600_dma_cs_next_reloc()
2452 			  idx, p->nrelocs);  in r600_dma_cs_next_reloc()
2455 	*cs_reloc = &p->relocs[idx];  in r600_dma_cs_next_reloc()
2479 	u32 idx, idx_value;  in r600_dma_cs_parse()  local
2484 		if (p->idx >= ib_chunk->length_dw) {  in r600_dma_cs_parse()
2486 				  p->idx, ib_chunk->length_dw);  in r600_dma_cs_parse()
2489 		idx = p->idx;  in r600_dma_cs_parse()
2490 		header = radeon_get_ib_value(p, idx);  in r600_dma_cs_parse()
2503 				dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2506 				ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);  in r600_dma_cs_parse()
2507 				p->idx += count + 5;  in r600_dma_cs_parse()
2509 				dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2510 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;  in r600_dma_cs_parse()
2512 				ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2513 				ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2514 				p->idx += count + 3;  in r600_dma_cs_parse()
2534 				idx_value = radeon_get_ib_value(p, idx + 2);  in r600_dma_cs_parse()
2538 					src_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2540 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in r600_dma_cs_parse()
2542 					dst_offset = radeon_get_ib_value(p, idx+5);  in r600_dma_cs_parse()
2543 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;  in r600_dma_cs_parse()
2544 					ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2545 					ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2548 					src_offset = radeon_get_ib_value(p, idx+5);  in r600_dma_cs_parse()
2549 					src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;  in r600_dma_cs_parse()
2550 					ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2551 					ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2553 					dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2555 					ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);  in r600_dma_cs_parse()
2557 				p->idx += 7;  in r600_dma_cs_parse()
2560 					src_offset = radeon_get_ib_value(p, idx+2);  in r600_dma_cs_parse()
2561 					src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in r600_dma_cs_parse()
2562 					dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2563 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;  in r600_dma_cs_parse()
2565 					ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2566 					ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2567 					ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2568 					ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2569 					p->idx += 5;  in r600_dma_cs_parse()
2571 					src_offset = radeon_get_ib_value(p, idx+2);  in r600_dma_cs_parse()
2572 					src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;  in r600_dma_cs_parse()
2573 					dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2574 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;  in r600_dma_cs_parse()
2576 					ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2577 					ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2578 					ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2579 					ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16;  in r600_dma_cs_parse()
2580 					p->idx += 4;  in r600_dma_cs_parse()
2604 			dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2605 			dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;  in r600_dma_cs_parse()
2611 			ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2612 			ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;  in r600_dma_cs_parse()
2613 			p->idx += 4;  in r600_dma_cs_parse()
2616 			p->idx += 1;  in r600_dma_cs_parse()
2619 			DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);  in r600_dma_cs_parse()
2622 	} while (p->idx < p->chunk_ib->length_dw);  in r600_dma_cs_parse()