Lines Matching refs:pll
981 void radeon_compute_pll_avivo(struct radeon_pll *pll, in radeon_compute_pll_avivo() argument
989 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? in radeon_compute_pll_avivo()
999 fb_div_min = pll->min_feedback_div; in radeon_compute_pll_avivo()
1000 fb_div_max = pll->max_feedback_div; in radeon_compute_pll_avivo()
1002 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_avivo()
1008 if (pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_avivo()
1009 ref_div_min = pll->reference_div; in radeon_compute_pll_avivo()
1011 ref_div_min = pll->min_ref_div; in radeon_compute_pll_avivo()
1013 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && in radeon_compute_pll_avivo()
1014 pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_avivo()
1015 ref_div_max = pll->reference_div; in radeon_compute_pll_avivo()
1016 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) in radeon_compute_pll_avivo()
1018 ref_div_max = min(pll->max_ref_div, 7u); in radeon_compute_pll_avivo()
1020 ref_div_max = pll->max_ref_div; in radeon_compute_pll_avivo()
1023 if (pll->flags & RADEON_PLL_USE_POST_DIV) { in radeon_compute_pll_avivo()
1024 post_div_min = pll->post_div; in radeon_compute_pll_avivo()
1025 post_div_max = pll->post_div; in radeon_compute_pll_avivo()
1029 if (pll->flags & RADEON_PLL_IS_LCD) { in radeon_compute_pll_avivo()
1030 vco_min = pll->lcd_pll_out_min; in radeon_compute_pll_avivo()
1031 vco_max = pll->lcd_pll_out_max; in radeon_compute_pll_avivo()
1033 vco_min = pll->pll_out_min; in radeon_compute_pll_avivo()
1034 vco_max = pll->pll_out_max; in radeon_compute_pll_avivo()
1037 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_avivo()
1045 if (post_div_min < pll->min_post_div) in radeon_compute_pll_avivo()
1046 post_div_min = pll->min_post_div; in radeon_compute_pll_avivo()
1051 if (post_div_max > pll->max_post_div) in radeon_compute_pll_avivo()
1052 post_div_max = pll->max_post_div; in radeon_compute_pll_avivo()
1057 den = pll->reference_freq; in radeon_compute_pll_avivo()
1063 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) in radeon_compute_pll_avivo()
1073 diff = abs(target_clock - (pll->reference_freq * fb_div) / in radeon_compute_pll_avivo()
1077 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { in radeon_compute_pll_avivo()
1094 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { in radeon_compute_pll_avivo()
1104 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_avivo()
1112 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + in radeon_compute_pll_avivo()
1113 (pll->reference_freq * *frac_fb_div_p)) / in radeon_compute_pll_avivo()
1134 void radeon_compute_pll_legacy(struct radeon_pll *pll, in radeon_compute_pll_legacy() argument
1142 uint32_t min_ref_div = pll->min_ref_div; in radeon_compute_pll_legacy()
1143 uint32_t max_ref_div = pll->max_ref_div; in radeon_compute_pll_legacy()
1144 uint32_t min_post_div = pll->min_post_div; in radeon_compute_pll_legacy()
1145 uint32_t max_post_div = pll->max_post_div; in radeon_compute_pll_legacy()
1148 uint32_t best_vco = pll->best_vco; in radeon_compute_pll_legacy()
1159 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); in radeon_compute_pll_legacy()
1162 if (pll->flags & RADEON_PLL_IS_LCD) { in radeon_compute_pll_legacy()
1163 pll_out_min = pll->lcd_pll_out_min; in radeon_compute_pll_legacy()
1164 pll_out_max = pll->lcd_pll_out_max; in radeon_compute_pll_legacy()
1166 pll_out_min = pll->pll_out_min; in radeon_compute_pll_legacy()
1167 pll_out_max = pll->pll_out_max; in radeon_compute_pll_legacy()
1173 if (pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_legacy()
1174 min_ref_div = max_ref_div = pll->reference_div; in radeon_compute_pll_legacy()
1178 uint32_t pll_in = pll->reference_freq / mid; in radeon_compute_pll_legacy()
1179 if (pll_in < pll->pll_in_min) in radeon_compute_pll_legacy()
1181 else if (pll_in > pll->pll_in_max) in radeon_compute_pll_legacy()
1188 if (pll->flags & RADEON_PLL_USE_POST_DIV) in radeon_compute_pll_legacy()
1189 min_post_div = max_post_div = pll->post_div; in radeon_compute_pll_legacy()
1191 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_legacy()
1192 min_fractional_feed_div = pll->min_frac_feedback_div; in radeon_compute_pll_legacy()
1193 max_fractional_feed_div = pll->max_frac_feedback_div; in radeon_compute_pll_legacy()
1199 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) in radeon_compute_pll_legacy()
1203 if (pll->flags & RADEON_PLL_LEGACY) { in radeon_compute_pll_legacy()
1217 uint32_t pll_in = pll->reference_freq / ref_div; in radeon_compute_pll_legacy()
1218 uint32_t min_feed_div = pll->min_feedback_div; in radeon_compute_pll_legacy()
1219 uint32_t max_feed_div = pll->max_feedback_div + 1; in radeon_compute_pll_legacy()
1221 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) in radeon_compute_pll_legacy()
1233 tmp = (uint64_t)pll->reference_freq * feedback_div; in radeon_compute_pll_legacy()
1246 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; in radeon_compute_pll_legacy()
1247 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; in radeon_compute_pll_legacy()
1250 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { in radeon_compute_pll_legacy()
1279 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || in radeon_compute_pll_legacy()
1280 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || in radeon_compute_pll_legacy()
1281 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || in radeon_compute_pll_legacy()
1282 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || in radeon_compute_pll_legacy()
1283 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || in radeon_compute_pll_legacy()
1284 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { in radeon_compute_pll_legacy()