Lines Matching refs:DMA0_REGISTER_OFFSET
1287 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): in si_get_allowed_info_register()
3279 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
3799 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); in si_gpu_check_soft_reset()
3881 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_soft_reset()
3883 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
4048 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4050 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
5526 offset = DMA0_REGISTER_OFFSET; in si_enable_dma_mgcg()
5538 offset = DMA0_REGISTER_OFFSET; in si_enable_dma_mgcg()
5944 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5945 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
6099 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set()
6186 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); in si_irq_set()