Lines Matching refs:DMA1_REGISTER_OFFSET
1288 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET): in si_get_allowed_info_register()
3280 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
3804 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); in si_gpu_check_soft_reset()
3887 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_soft_reset()
3889 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
4052 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4054 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
5528 offset = DMA1_REGISTER_OFFSET; in si_enable_dma_mgcg()
5540 offset = DMA1_REGISTER_OFFSET; in si_enable_dma_mgcg()
5946 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5947 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
6100 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set()
6187 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); in si_irq_set()