Lines Matching refs:WREG32_P
6787 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); in si_irq_process()
7328 WREG32_P(CG_UPLL_FUNC_CNTL_2, in si_set_uvd_clocks()
7333 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); in si_set_uvd_clocks()
7347 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); in si_set_uvd_clocks()
7350 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); in si_set_uvd_clocks()
7353 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); in si_set_uvd_clocks()
7356 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7365 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7368 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); in si_set_uvd_clocks()
7371 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in si_set_uvd_clocks()
7374 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK); in si_set_uvd_clocks()
7377 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9); in si_set_uvd_clocks()
7379 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9); in si_set_uvd_clocks()
7382 WREG32_P(CG_UPLL_FUNC_CNTL_2, in si_set_uvd_clocks()
7390 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7395 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in si_set_uvd_clocks()
7402 WREG32_P(CG_UPLL_FUNC_CNTL_2, in si_set_uvd_clocks()