3467 			radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);  in si_cp_enable()
3766 		radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);  in si_cp_resume()
4158 	       rdev->mc.vram_start >> 12);  in si_mc_program()
4160 	       rdev->mc.vram_end >> 12);  in si_mc_program()
4163 	tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;  in si_mc_program()
4164 	tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);  in si_mc_program()
4167 	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));  in si_mc_program()
4185 			  struct radeon_mc *mc)  in si_vram_gtt_location()  argument
4187 	if (mc->mc_vram_size > 0xFFC0000000ULL) {  in si_vram_gtt_location()
4190 		mc->real_vram_size = 0xFFC0000000ULL;  in si_vram_gtt_location()
4191 		mc->mc_vram_size = 0xFFC0000000ULL;  in si_vram_gtt_location()
4193 	radeon_vram_location(rdev, &rdev->mc, 0);  in si_vram_gtt_location()
4194 	rdev->mc.gtt_base_align = 0;  in si_vram_gtt_location()
4195 	radeon_gtt_location(rdev, mc);  in si_vram_gtt_location()
4204 	rdev->mc.vram_is_ddr = true;  in si_mc_init()
4244 	rdev->mc.vram_width = numchan * chansize;  in si_mc_init()
4246 	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);  in si_mc_init()
4247 	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);  in si_mc_init()
4256 	rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL;  in si_mc_init()
4257 	rdev->mc.real_vram_size = rdev->mc.mc_vram_size;  in si_mc_init()
4258 	rdev->mc.visible_vram_size = rdev->mc.aper_size;  in si_mc_init()
4259 	si_vram_gtt_location(rdev, &rdev->mc);  in si_mc_init()
4308 	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);  in si_pcie_gart_enable()
4309 	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);  in si_pcie_gart_enable()
4359 		 (unsigned)(rdev->mc.gtt_size >> 20),  in si_pcie_gart_enable()