Lines Matching refs:tegra_dc_writel
99 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
101 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
121 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
122 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
260 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); in tegra_dc_setup_window()
262 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH); in tegra_dc_setup_window()
263 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP); in tegra_dc_setup_window()
266 tegra_dc_writel(dc, value, DC_WIN_POSITION); in tegra_dc_setup_window()
269 tegra_dc_writel(dc, value, DC_WIN_SIZE); in tegra_dc_setup_window()
277 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); in tegra_dc_setup_window()
290 tegra_dc_writel(dc, value, DC_WIN_DDA_INC); in tegra_dc_setup_window()
295 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); in tegra_dc_setup_window()
296 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); in tegra_dc_setup_window()
298 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); in tegra_dc_setup_window()
299 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); in tegra_dc_setup_window()
301 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR); in tegra_dc_setup_window()
304 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U); in tegra_dc_setup_window()
305 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V); in tegra_dc_setup_window()
307 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE); in tegra_dc_setup_window()
309 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE); in tegra_dc_setup_window()
315 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); in tegra_dc_setup_window()
316 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); in tegra_dc_setup_window()
336 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); in tegra_dc_setup_window()
357 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); in tegra_dc_setup_window()
364 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF); in tegra_dc_setup_window()
365 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB); in tegra_dc_setup_window()
366 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR); in tegra_dc_setup_window()
367 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR); in tegra_dc_setup_window()
368 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG); in tegra_dc_setup_window()
369 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG); in tegra_dc_setup_window()
370 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB); in tegra_dc_setup_window()
371 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB); in tegra_dc_setup_window()
381 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); in tegra_dc_setup_window()
387 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY); in tegra_dc_setup_window()
388 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN); in tegra_dc_setup_window()
392 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X); in tegra_dc_setup_window()
393 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); in tegra_dc_setup_window()
394 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); in tegra_dc_setup_window()
398 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); in tegra_dc_setup_window()
399 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); in tegra_dc_setup_window()
400 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); in tegra_dc_setup_window()
404 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); in tegra_dc_setup_window()
405 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y); in tegra_dc_setup_window()
406 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY); in tegra_dc_setup_window()
616 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); in tegra_plane_atomic_disable()
620 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); in tegra_plane_atomic_disable()
744 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); in tegra_cursor_atomic_update()
748 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); in tegra_cursor_atomic_update()
754 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_update()
763 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_cursor_atomic_update()
767 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); in tegra_cursor_atomic_update()
784 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
935 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
948 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
972 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); in tegra_dc_finish_page_flip()
973 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_finish_page_flip()
975 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_finish_page_flip()
1071 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); in tegra_dc_set_timings()
1074 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); in tegra_dc_set_timings()
1078 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); in tegra_dc_set_timings()
1082 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); in tegra_dc_set_timings()
1086 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); in tegra_dc_set_timings()
1089 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); in tegra_dc_set_timings()
1154 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); in tegra_dc_commit_state()
1164 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1228 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_disable()
1251 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_enable()
1257 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_enable()
1262 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_enable()
1296 tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1297 tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1314 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); in tegra_dc_irq()
1601 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1610 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1778 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); in tegra_dc_init()
1781 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); in tegra_dc_init()
1786 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_dc_init()
1790 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_dc_init()
1795 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); in tegra_dc_init()
1799 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); in tegra_dc_init()
1803 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_dc_init()
1807 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_init()
1810 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); in tegra_dc_init()