47 #define S3C2410_IICCON			0x00  macro
207 	tmp = readl(i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_disable_ack()
208 	writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_disable_ack()
215 	tmp = readl(i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_enable_ack()
216 	writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_enable_ack()
225 	tmp = readl(i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_disable_irq()
226 	writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_disable_irq()
233 	tmp = readl(i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_enable_irq()
234 	writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_enable_irq()
242 		if (readl(i2c->regs + S3C2410_IICCON)  in is_ack()
281 	iiccon = readl(i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_message_start()
293 	writel(iiccon, i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_message_start()
564 	tmp = readl(i2c->regs + S3C2410_IICCON);  in i2c_s3c_irq_nextbyte()
566 	writel(tmp, i2c->regs + S3C2410_IICCON);  in i2c_s3c_irq_nextbyte()
592 		tmp = readl(i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_irq()
594 		writel(tmp, i2c->regs +  S3C2410_IICCON);  in s3c24xx_i2c_irq()
626 	tmp = readl(i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_disable_bus()
629 	writel(tmp, i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_disable_bus()
892 	iiccon = readl(i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_clockrate()
902 	writel(iiccon, i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_clockrate()
1054 	writel(0, i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_init()
1068 		readl(i2c->regs + S3C2410_IICCON));  in s3c24xx_i2c_init()