Lines Matching refs:tlbi
468 } tlbi; member
796 cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT; in arm_smmu_cmdq_build_cmd()
797 cmd[1] |= ent->tlbi.leaf ? CMDQ_TLBI_1_LEAF : 0; in arm_smmu_cmdq_build_cmd()
798 cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_VA_MASK; in arm_smmu_cmdq_build_cmd()
801 cmd[0] |= (u64)ent->tlbi.vmid << CMDQ_TLBI_0_VMID_SHIFT; in arm_smmu_cmdq_build_cmd()
802 cmd[1] |= ent->tlbi.leaf ? CMDQ_TLBI_1_LEAF : 0; in arm_smmu_cmdq_build_cmd()
803 cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_IPA_MASK; in arm_smmu_cmdq_build_cmd()
806 cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT; in arm_smmu_cmdq_build_cmd()
809 cmd[0] |= (u64)ent->tlbi.vmid << CMDQ_TLBI_0_VMID_SHIFT; in arm_smmu_cmdq_build_cmd()
1326 cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; in arm_smmu_tlb_inv_context()
1327 cmd.tlbi.vmid = 0; in arm_smmu_tlb_inv_context()
1330 cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; in arm_smmu_tlb_inv_context()
1343 .tlbi = { in arm_smmu_tlb_inv_range_nosync()
1351 cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; in arm_smmu_tlb_inv_range_nosync()
1354 cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; in arm_smmu_tlb_inv_range_nosync()