81 		irq_reg_writel(bgc, 0, AT91_AIC5_EOICR);  in aic5_handle()
97 	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);  in aic5_mask()
98 	irq_reg_writel(gc, 1, AT91_AIC5_IDCR);  in aic5_mask()
114 	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);  in aic5_unmask()
115 	irq_reg_writel(gc, 1, AT91_AIC5_IECR);  in aic5_unmask()
127 	irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR);  in aic5_retrigger()
128 	irq_reg_writel(bgc, 1, AT91_AIC5_ISCR);  in aic5_retrigger()
142 	irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR);  in aic5_set_type()
146 		irq_reg_writel(bgc, smr, AT91_AIC5_SMR);  in aic5_set_type()
168 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_suspend()
170 			irq_reg_writel(bgc, 1, AT91_AIC5_IECR);  in aic5_suspend()
172 			irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);  in aic5_suspend()
192 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_resume()
194 			irq_reg_writel(bgc, 1, AT91_AIC5_IECR);  in aic5_resume()
196 			irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);  in aic5_resume()
211 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_pm_shutdown()
212 		irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);  in aic5_pm_shutdown()
213 		irq_reg_writel(bgc, 1, AT91_AIC5_ICCR);  in aic5_pm_shutdown()
233 		irq_reg_writel(gc, 0, AT91_AIC5_EOICR);  in aic5_hw_init()
240 	irq_reg_writel(gc, 0xffffffff, AT91_AIC5_SPU);  in aic5_hw_init()
243 	irq_reg_writel(gc, 0, AT91_AIC5_DCR);  in aic5_hw_init()
247 		irq_reg_writel(gc, i, AT91_AIC5_SSR);  in aic5_hw_init()
248 		irq_reg_writel(gc, i, AT91_AIC5_SVR);  in aic5_hw_init()
249 		irq_reg_writel(gc, 1, AT91_AIC5_IDCR);  in aic5_hw_init()
250 		irq_reg_writel(gc, 1, AT91_AIC5_ICCR);  in aic5_hw_init()
273 	irq_reg_writel(bgc, *out_hwirq, AT91_AIC5_SSR);  in aic5_irq_domain_xlate()
277 		irq_reg_writel(bgc, intspec[2] | smr, AT91_AIC5_SMR);  in aic5_irq_domain_xlate()