70 static int cx22700_writereg (struct cx22700_state* state, u8 reg, u8 data)  in cx22700_writereg()  function
115 		return cx22700_writereg (state, 0x09, val | 0x01);  in cx22700_set_inversion()
118 		return cx22700_writereg (state, 0x09, val & 0xfe);  in cx22700_set_inversion()
163 		cx22700_writereg (state, 0x09, cx22700_readreg (state, 0x09 | 0x10));  in cx22700_set_tps()
165 		cx22700_writereg (state, 0x09, cx22700_readreg (state, 0x09 & ~0x10));  in cx22700_set_tps()
170 	cx22700_writereg (state, 0x04, val);  in cx22700_set_tps()
178 	cx22700_writereg (state, 0x05, val);  in cx22700_set_tps()
183 	cx22700_writereg (state, 0x06, val);  in cx22700_set_tps()
185 	cx22700_writereg (state, 0x08, 0x04 | 0x02);  /* use user tps parameters */  in cx22700_set_tps()
186 	cx22700_writereg (state, 0x08, 0x04);         /* restart acquisition */  in cx22700_set_tps()
244 	cx22700_writereg (state, 0x00, 0x02);   /*  soft reset */  in cx22700_init()
245 	cx22700_writereg (state, 0x00, 0x00);  in cx22700_init()
250 		cx22700_writereg (state, init_tab[i], init_tab[i+1]);  in cx22700_init()
252 	cx22700_writereg (state, 0x00, 0x01);  in cx22700_init()
290 	cx22700_writereg (state, 0x0c, 0x00);  in cx22700_read_ber()
322 	cx22700_writereg (state, 0x0f, 0x00);  in cx22700_read_ucblocks()
332 	cx22700_writereg (state, 0x00, 0x02); /* XXX CHECKME: soft reset*/  in cx22700_set_frontend()
333 	cx22700_writereg (state, 0x00, 0x00);  in cx22700_set_frontend()
342 	cx22700_writereg (state, 0x37, 0x01);  /* PAL loop filter off */  in cx22700_set_frontend()
343 	cx22700_writereg (state, 0x00, 0x01);  /* restart acquire */  in cx22700_set_frontend()
363 		return cx22700_writereg(state, 0x0a, 0x00);  in cx22700_i2c_gate_ctrl()
365 		return cx22700_writereg(state, 0x0a, 0x01);  in cx22700_i2c_gate_ctrl()