174 static struct viu_reg reg_val;  variable
402 	reg_val.field_base_addr = videobuf_to_dma_contig(&buf->vb);  in buffer_activate()
405 		buf, buf->vb.i, (unsigned long)reg_val.field_base_addr);  in buffer_activate()
408 	reg_val.status_cfg = 0;  in buffer_activate()
412 		reg_val.status_cfg &= ~MODE_32BIT;  in buffer_activate()
413 		reg_val.dma_inc = buf->vb.width * 2;  in buffer_activate()
416 		reg_val.status_cfg |= MODE_32BIT;  in buffer_activate()
417 		reg_val.dma_inc = buf->vb.width * 4;  in buffer_activate()
426 	reg_val.picture_count = (buf->vb.height / 2) << 16 |  in buffer_activate()
429 	reg_val.status_cfg |= DMA_ACT | INT_DMA_END_EN | INT_FIELD_EN;  in buffer_activate()
436 		reg_val.dma_inc = 0;  in buffer_activate()
438 	out_be32(&vr->dma_inc, reg_val.dma_inc);  in buffer_activate()
439 	out_be32(&vr->picture_count, reg_val.picture_count);  in buffer_activate()
440 	out_be32(&vr->field_base_addr, reg_val.field_base_addr);  in buffer_activate()
710 	out_be32(&vr->field_base_addr, reg_val.field_base_addr);  in viu_activate_overlay()
711 	out_be32(&vr->dma_inc, reg_val.dma_inc);  in viu_activate_overlay()
712 	out_be32(&vr->picture_count, reg_val.picture_count);  in viu_activate_overlay()
722 	reg_val.status_cfg = 0;  in viu_setup_preview()
725 	reg_val.picture_count = (fh->win.w.height / 2) << 16 |  in viu_setup_preview()
732 		reg_val.status_cfg &= ~MODE_32BIT;  in viu_setup_preview()
733 		reg_val.dma_inc = fh->win.w.width * 2;  in viu_setup_preview()
736 		reg_val.status_cfg |= MODE_32BIT;  in viu_setup_preview()
737 		reg_val.dma_inc = fh->win.w.width * 4;  in viu_setup_preview()
747 		reg_val.dma_inc = 0;  in viu_setup_preview()
749 	reg_val.status_cfg |= DMA_ACT | INT_DMA_END_EN | INT_FIELD_EN;  in viu_setup_preview()
752 	reg_val.field_base_addr = (u32)dev->ovbuf.base;  in viu_setup_preview()
1011 			u32 addr = reg_val.field_base_addr;  in viu_overlay_intr()
1015 				addr += reg_val.dma_inc;  in viu_overlay_intr()
1018 			out_be32(&vr->dma_inc, reg_val.dma_inc);  in viu_overlay_intr()
1022 				 reg_val.status_cfg);  in viu_overlay_intr()
1027 				 reg_val.status_cfg);  in viu_overlay_intr()
1066 			u32 addr = reg_val.field_base_addr;  in viu_capture_intr()
1069 				addr += reg_val.dma_inc;  in viu_capture_intr()
1074 			out_be32(&vr->dma_inc, reg_val.dma_inc);  in viu_capture_intr()
1078 				 reg_val.status_cfg);  in viu_capture_intr()