Lines Matching refs:asic3_read_register
99 u32 asic3_read_register(struct asic3 *asic, unsigned int reg) in asic3_read_register() function
104 EXPORT_SYMBOL_GPL(asic3_read_register);
112 val = asic3_read_register(asic, reg); in asic3_set_register()
133 edge = asic3_read_register(asic, in asic3_irq_flip_edge()
155 status = asic3_read_register(asic, in asic3_irq_demux()
172 istat = asic3_read_register(asic, in asic3_irq_demux()
235 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); in asic3_mask_gpio_irq()
248 regval = asic3_read_register(asic, in asic3_mask_irq()
272 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); in asic3_unmask_gpio_irq()
285 regval = asic3_read_register(asic, in asic3_unmask_irq()
311 level = asic3_read_register(asic, in asic3_gpio_irq_type()
313 edge = asic3_read_register(asic, in asic3_gpio_irq_type()
315 trigger = asic3_read_register(asic, in asic3_gpio_irq_type()
461 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION); in asic3_gpio_direction()
505 return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask; in asic3_gpio_get()
529 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT); in asic3_gpio_set()
618 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); in asic3_clk_enable()
634 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); in asic3_clk_disable()